xxxajk

Yeah, but can the last (TAIL) TCD point to the first (HEAD) TCD automatically? The terse example from NXP (AN14300) just has two tiny chunks, and from what I understand, fires once, and stops. It's not even clear what the struct actually looks...

It is totally contiguous, long list? That's totally fine, especially if I can point the tail back to the head an loop it. of the DMAMEM's 512K, there would be a maximum of two 200,000 byte buffers so: 524288-400000=124288 byes of DMAMEM left over...

Doing more datasheet reading, and wouldn't using scatter/gather with a looping list do what I need from a single channel?

In any case, once working, and because cache coherency doesn't matter until I manually halt the loop (to inspect it), where I would end up using DMA (again) to copy to a PSRAM block later on. Eventually I will be needing to do 2 of these loop...

Excellent. So you trigger a DMA to program a DMA from a linked list... I like it. (or are you just chaining DMA...) Got an example? Sizes I'd need are 25000, 50000, 100000 and 200000, ideally just the last two...

6.4.4.3 ... a circular data queue in which the size of the queue is a power of 2... ugh :-)

got it, needed i.MX RT1060 Processor Reference Manual, Rev. 3, 07/2021

Which date is the RM? i.MX RT1060X Processor Reference Manual, Rev. 1, 05/2022 stops at 6.5.5.3...

Two PRs submitted for cores (#784) and LittleFS (#60). Tested with one or two 16MB PSRAM parts, and one plus a QSPI Flash.

Already went through the DMA in the core... what's odd is that: 1: it accepts counts that can be too high 2: Seems to be able to do 65535 transactions maximum on T4.1 (T4.0? dunno, might check that, should be the same?) 3: the excessive counts...

Yeah, memory -> spi (loop back to) spi -> memory. can't use larger words either, unfortunately, since that would impose too much latency, where the output will actually be sometimes modified and looped back. Think of it as thus: I have a bit...

Noticing that if I try and do a DMA transfer to/from SPI to DMAMEM that if the transfer > 64K I end up with garbage on the output, and no clue if the input is corrupting anything. So the question is, _WITHOUT_ using any ISRs, how can I do a...

I will reach out to SparkFun.

Perhaps someone should alert Spark Fun about the availability/opportunity. Certainly they'd have some ability to order quantity with enough buying power.

I've got hold of a few IS66WVS16M8FBLL chips (3.3V 16MByte), and have managed to get the cores to initialise them correctly. Two of them show up as 32MB, and the standard PSRAM test passes. I don't have a lot of Teensy 4.1s knocking about, so the...

Fantastic!!! So basically it works??

Have none yet myself. The code to operate these are based on the datasheet. Been also looking into using 8bit wide PSRAM via an adapter... Hmmmm :)

...or stolen from unused section, which is what I do on MIPS with NVIC...

Yeah, the only thing I find disappointing, is as far as hack value is that the 32bits don't roll over, but are lost or masked, so it's as if something useful like that was engineered out of it? 🤔 As for the whole clocking thing, I don't know how...

Full logic example on FLEXIO2. Hopefully it helps people understand how to at least use FlexIO2/shifter4 @jmarsh Whadoyathink? #include <Arduino.h> /* Instructions for wiring: * INPUTS A and B * connect button to pin 6 to ground, this is...

Good news is you can output on a bit higher, but the bad news is the selection doesn't wrap... E.G. input for shifter 4, can't reference any bits before bit 09! The output is always base IO + 1, which almost makes sense, but on AVR it is legal to...

Yep! That was the whole problem! Me being stupid :-) For my next trick, I'm going to see if I can force the output to appear on GPIO_B0_00 :)

On a regular CCL LUT, each bit is output from a bit indexed in the "truth" byte, which has 3 inputs. 3 bits 8 locations... So wouldn't XOR be: * I I I I I O * N N N N N U * 4 3 2 1 0 T * 00 0...

Come to think of it, I wonder if the logic "truth" value is looking at the wrong sequences

@jmarsh Doesn't work, documentation is crappy/unhelpful, or I am plain stupid? CCM_CCGR3 |= CCM_CCGR3_FLEXIO2(CCM_CCGR_ON); FLEXIO2_CTRL |= FLEXIO_CTRL_FLEXEN; IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = FLEXIO2_ALT_MODE; //...

Fantastic! Thank you so much. I get what the comments say about most of the stuff, mentions "timer" stuff, but I know what the comment actually means. I'll write some full examples (I'll document it differently/better) and post them here for...

So, almost as good as the AVR implementation... interesting. Deal is that on the AVR, there's extra stuff you can do, such as D-flipflop's in-line with the input to artificially delay a signal, and even a flipflop you can use, all with any kind...

@jmarsh Out of curiosity with flexio, do you happen to know what the P->Q latency is for some simple logic? Is it clocked, or is it fully independent of any of the various SoC clocks? I'm asking because I can get under 6nS latency if I don't do...

Considering how pins need to be consecutive, I broke them down into useful groups. Now, if I have the pin->pad->alt assigments right... Pin groups for Flexio are/should be: FlexIO pin pad UNUSABLE XXX 1 AD_B0_02...

One of the reasons I am interested in the logic mode, is because I can simplify the state machine part, plus the output needs to be steered. To explain: There is a "main steering" signal that says data is starting to flow either in or out. The...

I'm fine with fixed, And if it works on one, then it's a simple matter to use the second one... I'll use which ever mode makes sense. Here are some scope shots from the raw output as in raw from analog, before it is corrected to levels for...

I have an analog front-end pre-processor that has 4 outputs. The outputs are pretty stupid, and signals can end up stretched. The timing is very tight... I could use the usual 74xxx logic to get what I need, and infact did that. I could do it in...

That is the full circuit, v+ is your 3.3v protected output.

Sure, here's one. NOTES: SCR trip voltage is 400mV, you may need to adjust R1 to a lower value to decrease sensitivity. volts D1 R1 trips at 3.3v 1N5333 60K 3.49V 5.0v 1N5228 60K 6.09V

You are quite welcome. If you need a schematic for the crowbar circuit, let me know.

Tips for a bulletproof setup: Use a poly fuse at least for low current applications, or a miniature circuit breaker for more demanding amps. When dealing with higher voltages than the MCU, the safest thing to do is use optical isolation. Both...

That's where you use a bidirectional transceiver IC that does dual voltage and doesn't require the DIR pin. I've done something similar with optoisolators to achieve the same effect for 3.3v <--> 5v single-wire interfaces manually. The other way...

Actually, possible, with adapting it. Give chip 1.8v, and use zener+resistors to clamp i/o ;-)

APS12804O-SQRH-SN is an option... everything it seems is dropping to 1.8v these days... ugh.

No, 32mBYTE is correct. The interface can support up to 512MBytes total as-per the data sheet. All depends on what's out there, and what is adaptable, e.g. there's BGA variants that could be adapted on a thin adapter board.

It's available as the ALL part I believe, which (while it violates voltages) should work just like the 8MB part did, hopefully. If it smokes, I'm only out a few dollars... There's also other PSRAM vendors as well... I just haven't looked around...

Yeah I DO plan on getting and testing the 16MB part. Will be nice I suppose to have 16MB RAM *AND* flash at the same time.

Then, perhaps LittleFS needs to look at that register? Sorry if that broke it. Never used or needed to use LittleFS considering there's USB and SD for storage, and that I use my own implementation for both. However that doesn't mean I do not see...

OOF! Sorry I poked the hornet's nest :) I didn't do any modifications that would break things, however I do think that instead of using the uint8_t for the ram size in MB, that instead you should look at the two registers provided, and when...

PR is here: https://github.com/PaulStoffregen/cores/pull/782

It is what I happened to have on hand. BLL should work too. i think ISSI does binning based on the lowest voltage the chip can work at. The maximum voltages are still 3.6v on both, so technically no spec is violated.

I have some ISSI PSRAM that is perfectly compatible with Teensy4.1 when the ISSI ID is checked, and you can even mix the two. The ISSI PSRAM part number I tested is IS66WVR8M8FALL-104NLI and the ID for it is 0x5D9D. (Yes this is a 1.9v part, but...