External Clock Generation on Teensy MicroMod

[twestendorf]

Hello, first time posting here!

Pretty new to using Teensy and have been running into an issue when trying to generate a couple clock signals. For context, I am using the Teensy MicroMod board connected to a MicroMod ATP carrier board. The project is setup using VisualTeensy and I have been using a Saleae logic pro 8 logic analyzer to examine the output from the two output pins corresponding to CLKO1_CLK and CLKO2_CLK on the microcontroller. I am just trying to generate a 2^20 Hz (~1.04 MHz) clock signal on CLKO2_CLK and a 4096 Hz signal on CLKO1_CLK. The low-speed clock (4096 Hz) seems to be working as expected, but the higher speed clock results are a little faster than expected.

To help get started I used the NXP Clocks Config Tool to see how the clocks could be generated and ended up with the plan to use SAI1_CLK_ROOT as the source for CLKO2 and CKIL_SYNC_CLK_ROOT as the source for CLKO1 (divided down by 7 and 8, respectively). For the SAI1_CLK_ROOT I selected the PLL3_PFD2_CLK which is shown to be 411.42 MHz by the config tool, but the values I am measuring on my logic analyzer are not making sense (Is this changed in startup code or something?). The images below show the configuration I am trying to accomplish, but I have a feeling the signal coming out of the PLL is not what I think it is...

Here is the code I am using to set up the clocks along with the results I am seeing on the Saleae:

void setup()
{
    // initialize serial port
    Serial.begin(115200);

    // configure output clocks
    // MUX GPIO_SD_B0_04 to be HS clock output (ALT6)
    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 0b110;
    // MUX GPIO_SD_B0_05 to be LS clock output (ALT6)
    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 0b110;

    // set up SAI1 clock
    CCM_CSCMR1 |=
        CCM_CSCMR1_SAI1_CLK_SEL(00); // SAI1_CLK_SEL = PLL3_PFD2_CLK (411.42MHz)
    CCM_CS1CDR |= CCM_CS1CDR_SAI1_CLK_PRED(
        0b110); // SAI1_CLK_PRED = 0b110 (divide by 7 = 58.77 MHz)
    CCM_CS1CDR |= CCM_CS1CDR_SAI1_CLK_PODF(
        0b000111); // SAI1_CLK_PODF = 0b000111 (divide by 8 = 7.34MHz)
    CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); // enable SAI1 clk

    // configure CLKO1 and CLKO2
    CCM_CCOSR = 0x00000000;                  // clear CCM_CCOSR register
    CCM_CCOSR |= CCM_CCOSR_CLKO2_DIV(0b110); // divide CLKO2_CLK by 7
    CCM_CCOSR |=
        CCM_CCOSR_CLKO2_SEL(0b10010);    // SAI1_CLK_ROOT as source for CLKO2
    CCM_CCOSR |= !CCM_CCOSR_CLK_OUT_SEL; // select CLK01_CLK source
    CCM_CCOSR |= CCM_CCOSR_CLKO1_DIV(0b111); // divide CLKO1_CLK by 8
    CCM_CCOSR |=
        CCM_CCOSR_CLKO1_SEL(0b1110); // ckil_sync_clk_root as source for CLKO1
    CCM_CCOSR |=
        CCM_CCOSR_CLKO2_EN | CCM_CCOSR_CLKO1_EN; // enable Clock outputs
}

Am I missing something with setting up these clocks? Any help tracking this down would be appreciated, thanks!

 

[twestendorf]

One step forward and two steps back... Messing around with the clocks tool again I noticed that the PLL3_PFD2 divider value changed automatically while I was entering values. I was unaware that was configurable! It most likely got adjusted away from the default value while I was setting up the initial configuration leading to a different clock value coming from PLL3_PFD2 than I was expecting. I also discovered that the tool rounded the requested 1.048576 MHz to 360/343 MHz. This leads to a new problem since I need the HS clock to be as close to 2^20 Hz as possible... any ideas on how to achieve this? Will I have to sacrifice a timer module to divide the clock down as accurately as needed?

 

[twestendorf]

I think I have since been able to sort this out. Generating an approximate 2^20 Hz clock on CLKO2 pin. Should be good enough for what I am using it for, at least for a while.