sicco

The benefits are: * More i/o pins remain available for other use * Fewer wires to so lower cost and lower likelihood of wiring errors * Impossible to mixup input, output, tx, rx pins… But don’t forget the GND wire. There’s no such thing as 1 wire…

A gnss module maybe? The 1 pulse per second output on legacy gps modules used to be pretty accurate already, and a UTC timestamp is given for free. Works indoors also nowadays with Galileo.

I connected a scope and checked if the Teensy 4.1 PSRAM power-up initialization timing is as per Adafruit IC PSRAM 64Mbit SPI 133MHz 8-SOIC 'shoulds' in datasheet, ref datasheet page above. It does not. I see ~20 ms in between VDD active and CE#...

The datasheet says it does matter… And what about the 150 us? Is that respected? And keeping CLK low while /CE remains high - does it really do that? I mean how can it do that when pullups or pulldowns are still off? Think also what might...

Ok, but reset state for the pin weak internal pullup is ‘off’. So what is it in the hardware that assures us that in between power on (or any) reset and executing the quoted initialisation code the /CS levels are really high? And follow VDD when...

Is the problem still there after hard wiring a pullup resistor, say 100k, from VDD to Adafruit IC PSRAM /CS? Reason for asking: when Teensy boots and searches for what might be soldered in the optional PSRAM and Flash, it may not have pulled high...