Hi Paul,
Thanks for your reply. I know you're busy with the new board, and that's pretty exciting!
Yes I have a dual-channel 100Mhz scope (Tektronix, I'm from Beaverton after all) and have been experimenting with various registers, primarily in output_i2s.cpp.
If I change the bit clock divider (I2S_TCR2_DIV and I2S_RCR2_DIV) from 3 to 1 I get a BCLK at 2.82Mhz, i.e. 64x Fs. So that's promising. But the LRCLK also doubles to 88.2kHz, hmm. Tried increasing I2S_TCR4_SYWD to 31, but it can't be bigger than the word size.
Next I changed CORE_PIN11_CONFIG to output the RX BCLK, and now have a 44.1kHz LRCLK on pin 23 and a 2.82Mhz BCLK on pin11. Don't think I need MCLK in our product so maybe this hack will get me going.
One thing I noticed that may be more generally salient, is that the default output_i2s.cpp sets both TX and RX as synchronous (I2S_xxR2_SYNC = 1). The K20 manual sez that if either one of the SAI TX or RX is synchronous, the other must be asynchronous. When I changed that, the 88.2kHz BCLK become a lot less jittery, fwtw.
Code:
// configure transmitter
I2S0_TMR = 0;
I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
I2S0_TCR2 = I2S_TCR2_SYNC(1) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
// | I2S_TCR2_BCD | I2S_TCR2_DIV(3);
| I2S_TCR2_BCD | I2S_TCR2_DIV(1);
I2S0_TCR3 = I2S_TCR3_TCE;
I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
// configure receiver (sync'd to transmitter clocks)
I2S0_RMR = 0;
I2S0_RCR1 = I2S_RCR1_RFW(1);
// I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
I2S0_RCR2 = I2S_RCR2_SYNC(0) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1) //see p.1314 of K20 manual--
// | I2S_RCR2_BCD | I2S_RCR2_DIV(3);
| I2S_RCR2_BCD | I2S_RCR2_DIV(3);
I2S0_RCR3 = I2S_RCR3_RCE;
// I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF //nice try, SYWD must be less than WNW
I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
// configure pin mux for 3 clock signals
CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
// CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
CORE_PIN11_CONFIG = PORT_PCR_MUX(4); // pin 11, PTC6, I2S0_RX_BCLK
It prolly shows, I have much more experience debugging hardware and interface firmware than DMA coding. I've had glimmers of increasing the wordlength, frame size, and/or sample rate and then masking off the extra bits so Teensy still sees stereo 16/44.1, but I haven't grokked how BCLK truly relates to FIFO DMA, etc. etc.
Happy to try any suggs, this is one of several new I2S projects so it's all good learning curve.
Thanks!
-alex