Some comments on circuits using the Analog Input

[DrM]

There are a lot of posts on this and many other forums that go something like "Why am I getting incorrect readings or weird behaviors from the analog input?"

And there are lots of responses that go something like, just use this code. If that code answer amounts to lengthen the "acquisition" step, it might work in certain cases. But in general the problem is electrical, not code, and it is fundamental to the kind of analog input that we have in microcontrollers including the Teensy and other Arduino family boards.

I wrote a longer post with illustrations in spice, you can read it here post on using a SAR adc with spice model illustrations

But, not everybody will click and it is such a recurring issue that maybe it is worthwhile to give a short synopsis here. Maybe some will take a look at the full post.

Lets start with those tutorials on using a thermistor with the analog input. I am not going to shame anyone, but lets say the "advise" often amounts to something like this.

(DON'T DO THIS!, well maybe but only if you also do... we'll take about it a moment)

So what is wrong? in a nutshell, the analog input is a SAR type ADC. The input pin is connected by a switch to a sampling capacitor, of about 30 or 40 pf. That 10k resistor prevents the sampling capacitor from being able to charge up to the input voltage before the end of the sampling window. (The value for the sampling capacitor will usually be in that range, it has to do with certain tradeoffs and the famous kT/C noise.)

This is part of a behavior known as kickback. But it is not just about reading the right voltage. There also can be spikes in whatever you attach to the input. So there are two behaviors, spikes and failure to read the right voltage.

Lets see how it works now in a more specific way.

Here is a SPICE model for the input stage for a SAR. It is a switched capacitor network. The first switch S1 connects the sampling capacitor C1 to the input. That is called the "acquisition" phase. Then S1 opens and switch S2 would normally connect the C1 to the conversion stage. That is called the "conversion" phase. Here S2 grounds the capacitor to clear it for the next clock cycle (we are studying the input for this discussion).

Here is an important detail: The conversion stage sees the voltage on C1 at the end of the acquisition phase. If C1 has not charged up to the input voltage in that time, then the reading is not correct. Finished? Not quite.

Okay, let's connect the thermistor to this input and see what happens.

Oops! See the red curve, that is the voltage at the input. Notice the voltage drop, and it is still low at the end of the sampling window.

Just to be completely clear, here is the voltage on the sampling capacitor. It is like the figure you see in textbooks for charging a capacitor. Anyway, it is obviously not going to work very well when R x C is large or the time is short.

At this point, let's mention three ways to solve this.

The best solution is (a) use a buffer with an RC to act as charge reservoir. Next best, (b) at least use a buffer. And if you insist on direct connection of the divider to the analog input, you might get away with it if you can (c) lengthen the sampling window/

Regarding (c), if you want 1% accuracy, a 1.5usec window might work. Similarly, for 12 bits, then 3 usec. I believe the API for the ADC has a control to set the sampling window, I do not know how long it can be.

Okay lets look at actual solutions. Here is the best. It looks like an RC has been inserted between the opamp and the analog input. But this is not about filtering exactly. The point here is that C2 acts as a charge reservoir for C1. And C2 is replenished through R1. True, R1xC2 is a filter, and you can choose R1 like that, but C2 has to be bigger than C1 and R1 has to be small enough that the opamp is able to replenish C2.

Here is what the current flows look like. Notice the current for C1 comes from C2, and the replenishment of C2 through R1

So that is the best solution. Here is second best, an opamp follower with a small resistor in series. I added a trace for the input pin of the opamp. We see a spike on the output from the R1, that of course means there is a smaller spike on the feedback network and we even see a small spike on IN+. That spike on IN+ is not likely to have much current behind it, so you might get away with it. But there are a few parts that are more sensitive than others. So be mindful if you do it this way. (We should be mindful always anyway)

(One additional comment, that can be very important too: If you are going to do (a) or (b), please do make a soldered board. The parasitic impedance, with solderless breadboards and jumper wires inserted into the current flow for the sampling capacitor, is not helpful at typical sampling rates.)


Okay that is the short version.

Please do find a moment to read the full post if this is something that might help you: post on using an analog input with illustrations in spice

 

[DrM]

@Paul hi, hopefully this is helpful. I wasn't sure which to which forum it should be posted. Suggestions?

 

[MarkT]

And the simpler solution for a slow-changing analog input is to put 100nF or so to ground on the input pin - this will present a low impedance on the timescale of an ADC conversion, and is one extra component. Typical sampling caps in modern chips are only a few pF BTW, there isn't enough chip area for anything more, but the principles outlined above still apply - a low impedance source will prevent cross-talk between analog inputs and increase accuracy.

For fast changing signals this implies using a buffer as above, for slow signals a capacitor is a simpler solution I think. You have to beware of ceramic caps that are not NP0/C0G type, as they are microphonic and can pick up vibrations as false voltage signals.

 

[DrM]

@MarkT, could you show how that works? To check, you said 100nf from input to ground, right?

Like this???

It seems like 100nf means you now have a time constant of about 1msec. That would mean you now need order 10 milliseconds before the input will reach the right voltage.

In other words, it seems like you made the problem much worse, about a thousand times worse.


Am I missing something here?

Maybe you could show how it works in a spice model. I am attaching the ltspice model for the sar input model with thermistor for convenience.

On the other point, low value caps:

Do you have an example of a precision SAR ADC chip with a low value sampling cap?

As I understand it, the fundamental limit comes from kT/C noise. In fact there are a bunch of papers reporting work to try to get around that.

"A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier" 2023, https://ieeexplore.ieee.org/document/10121326

"A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation" 2020, https://ieeexplore.ieee.org/document/9177083

and etc.

But I agree that there are low value caps in some of the microcontrollers. I don;t how they do it, execpt perhaps if they do it slowly. (I would say they are also famously not very good ADCs, but lets try to understand whats going on). For example, the IMXRT1060 has 1.5pF and 5 to 25K in series with it.

Anyway, even 2pF is still not a game changed for kickback, as you noted, I think.

 

[DrM]

@MarkT - i see the confusion, it is not about a slow or fast changing signal, it is about the sampling window of the SAR.

You could say the switch makes it a fast changing signal, so-to-speak.

Notice that the spice model has a DC level on the divider. That is about as slow changing as it gets, or, one hopes so.

 

[DrM]

SPICE models for the Teensy4 ADC Input

@MarkT - this addresses the points you raised, I hope. The last figure I think might explain why that sampling cap is only 2pf, besides that it is only 12 bits. The Teensy3.2 had 10pf for 16 bit mode, and 2kohm in series.

@PaulStoffregen - thoughts?

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Attached to this post, are SPICE models for the SAR ADC input of the Teensy 4, using parameters from the IMXRT1060CEC data sheet.

I would have liked to add this to the original post, but it is not editable now, and for the other option, start another thread, I am not sure of protocols, So let's start here. Maybe @PaulStoffregen will suggest something if it is useful.


A. Some comments in preface:

1) The overarching point, is that it seems that what the manufacturer did, was to put a large resistor in series with the ADC to slow the kickback spike and reduce the current you need to supply. But, that often means that you have to use a longer sampling window to get a realistic reading.

2) I think they might have viewed that as something like "fool proofing". It lets it work after a fashion for those who might use a high valued resistor divider network as as an input to a switched capacitor sampling network (i.e, a SAR). But again, notice that they stipulate a maximum source resistance at 1kohms. The thermistor network of course is more than that. But as you will see, under some settings it sorta' can work anyway.

3) That resistor in series (inside the chip) actually spoils the input in some circumstances. There is a spice model showing that towards the end of this post. For precision work you are almost always better off with an external ADC.

B. Okay, now the spice models:

1) First, the settings selected:

The input resistor in the SAR and the conversion clock are selected together by ADLPC and ADHSC,

The sampling period is set by ADLSMP ADSTS, as a multiple of the period of the ADC async clock source 10MHz or 20MHz

For the demo, I chose the low and high values for the input resistor, and the fastest and a mid range value for the sampling period.

2) The results:

a) Without opamp buffer

Here is fast, fast. it sort of squeaks by, but there is going to be a small error in the reading.

Here is slow, fast. As you can see it doesn't work out very well. There will be a substantial voltage error in the readout.

And finally, slow, slow. This is what you need to do if you want to read the thermistor directly into the ADC input.

b) With buffer

Okay lets try to fix this up by adding a buffer.

Here is fast, fast, with an opamp buffer. It works better, it reaches the input votlage within about 1/5 of the sampling window. 1/10 would be better, but it might be okay for 12 bits. That 5k resistor, which is the smallest they have, is really really in the way of getting a nice short duration recovery in the sampling network. The interested reader can do the calculation.

And now, the piece of resistance as they say in french.

Here is slow, fast. That 25k resistor is completely out of the question if you want to drive the input in a sensible way. And since it is built into the chip, they really ruined the analog input for any sort of rational use.

And now we understand why it is a 2pf capacitor, besides that it is only 12 bits. But anyway, it's not a very good input.

 

[MarkT]

On a modern logic chip 2pF is a lot of area. The usual unit for measuring component capacitances on a VLSI chip is the femtofarad!

 

[DrM]

@MarkT, yes I appreciate the challenge. That is why there are researchers working on the kT/C noise challenge. Maybe some major breakthrough in dieliectrics will give us a smaller 10pf some day, or some other way to store charge linear in V will appear.

The mcu in the Teensy3.2 has a 10pf sampling capacitor for the 16 bit mode. That is sorta what you gotta have for the time being.

I think the answer, bottom line so to speak, is that if you want to do precision measurements (except perhaps super slow), you really have to use an external analog-digital convertor.

My brother (an instrumentation physicist) pointed out another interesting problem, some sensors have 1/f noise. Time doesn't help you in those cases. I might work up something for that, maybe with a sketch to actually implement the measurement technique for 1/f.