Teensy 4.1 Debug Mod Project

Yes, fully agree, can't wait, no being able to debug very difficult and a lot of extra work, I must simulate everything on PC first, including encoders, motors, LCD, key's ...
 
I'm using a J-LINK plus compact with the MOD on GND, and the teensy side of the flex connector connected to JTAG.
Using J-Flash V7.84f, with device , NXP MIMXRT1062xxx6B selected and the JTAG settings on Auto, I can connect. I get the following

Connecting ...
- Connecting via USB to probe/ programmer device 0
- Probe/ Programmer firmware: J-Link V11 compiled Jan 30 2023 11:22:20
- Probe/ Programmer S/N: 851005664
- Device "MIMXRT1062XXX6B" selected.
- InitTarget() start
- Failed to power up DAP.
- Executing Connect Under Reset
- Failed to power up DAP.
- Executing Connect Under Reset
- _TargetHalt: CPU halted
- InitTarget() end
- TotalIRLen = 4, IRPrint = 0x01
- JTAG chain detection found 1 devices:
- #0 Id: 0x0BA02477, IRLen: 04, CoreSight JTAG-DP
- DPIDR: 0x0BD11477
- CoreSight SoC-400 or earlier
- Scanning AP map to find all available APs
- AP[1]: Stopped AP scan as end of AP map has been reached
- AP[0]: AHB-AP (IDR: 0x04770041)
- Iterating through AP map to find AHB-AP to use
- AP[0]: Core found
- AP[0]: AHB-AP ROM base: 0xE00FD000
- CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
- Found Cortex-M7 r1p1, Little endian.
- FPUnit: 8 code (BP) slots and 0 literal slots
- CoreSight components:
- ROMTbl[0] @ E00FD000
- [0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
- ROMTbl[1] @ E00FE000
- [1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
- ROMTbl[2] @ E00FF000
- [2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
- [2][1]: E0001000 CID B105E00D PID 000BB002 DWT
- [2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
- [2][3]: E0000000 CID B105E00D PID 000BB001 ITM
- [1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
- [1][2]: E0042000 CID B105900D PID 004BB906 CTI
- [0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
- [0][2]: E0043000 CID B105F00D PID 001BB101 TSG
- Cache: Separate I- and D-cache.

- I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
- D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
- Target interface speed: 4000 kHz (Auto)
- VTarget = 3.277V
- InitTarget() start
- InitTarget() end
- TotalIRLen = 4, IRPrint = 0x01
- JTAG chain detection found 1 devices:
- #0 Id: 0x0BA02477, IRLen: 04, CoreSight JTAG-DP
- DPIDR: 0x0BD11477
- CoreSight SoC-400 or earlier
- AP map detection skipped. Manually configured AP map found.
- AP[0]: AHB-AP (IDR: Not set)
- AP[0]: Core found
- AP[0]: AHB-AP ROM base: 0xE00FD000
- CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
- Found Cortex-M7 r1p1, Little endian.
- FPUnit: 8 code (BP) slots and 0 literal slots
- CoreSight components:
- ROMTbl[0] @ E00FD000
- [0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
- ROMTbl[1] @ E00FE000
- [1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
- ROMTbl[2] @ E00FF000
- [2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
- [2][1]: E0001000 CID B105E00D PID 000BB002 DWT
- [2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
- [2][3]: E0000000 CID B105E00D PID 000BB001 ITM
- [1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
- [1][2]: E0042000 CID B105900D PID 004BB906 CTI
- [0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
- [0][2]: E0043000 CID B105F00D PID 001BB101 TSG
- Cache: Separate I- and D-cache.

- I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
- D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
- Executing init sequence ...
- Initialized successfully
- Target interface speed: 4000 kHz (Auto)
- Found 1 JTAG device. Core ID: 0x0BA02477 (None)
- Connected successfully

However, if I try to Flash a file that compiled in Arduino (just to blink the LED), I get

Screenshot 2023-02-08 181239.png
 
Apologies the flash I was using was not suitable.
This works and is excellent.
Thanks Spencer for all the effort that went into this!
 
Hi,
I wish to obtain or have manufactured the PCB designed by Spencez.
I've searched on OSHPark and can't find a share.
Could you tell me if it is possible?
THANKS.
 
https://github.com/SpenceV1/Teensy_41_Debug_PCB

There is a catch. It is designed for the original 16 pin bootloader chip. PJRC had to change the board for a different chip with a different footprint, to continue shipping, but I remember that the plan was to return to the original 16 pin package.
The modification takes some patience but it does work! Use a heat gun and some low temp solder.
 
Parasram said:
but I remember that the plan was to return to the original 16 pin package.
Click to expand...

Very difficult to predict the future in these times of supply chain shortages, but today all signs are looking like we'll keep using the new chip until at least 2024 or farther.

Teensy 4.0 and 4.1 are in stock today because we're planning and managing supply of all the parts *really* far into the future. The flip side is we won't be able to change back to the old chip for quite a while, even if NXP manages to ship our 2021 orders.
 
I took the trip down the Teensy debug rabbit hole by following Spencez'e excellent guide and Kicad files. I purchased several Teensy 4.1's from Amazon to serve as my guinea pigs. I converted the Kicad PCb files to Gerber using the instructions on the JLCPCB site since I had them make the flex and hard PCB. I did have to reduce the trace width on the flex PCB to 0.075mm to meet JLCPCB's solder mask clearance requirements.

I had trouble connecting to the board with a J-link Edu Mini. I spent a couple of days and a few PM's with Spencez trying to figure out why I could not connect. I ohm'ed out all the connections from the Teensy via's to the Jlink connector. Everything checked out. I opted not to cut the MOD trace. Well that turned out to be my issue. Once I cut the MOD trace, soldered the switch to the adapter PCB and set it to "N", I was able to connect. Many thanks to Spencez for the PM help and trailblazing as well as all the others on this forum.
 
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