@KurtE
In KurtE's FlexIO page at github, it seems to say the default clock rate for the FlexIO is 30MHz. And, it offers the following which seems to change the master clock for the FlexIO.
It seems like these arguments align with Figure 14-2. Clock tree part 1, the processor reference manual Rev 3, page 1010.
In the KurtE's FlexIOSPI there is a transaction call with a clock setting. Looking into the source code, it seems that a divider is constructed from the transaction setting and the above clock.
Now the question. In simplified terms, can a faster clock be set for the FlexIO SPI? How fast can it be? How exactly do we do that?
I would like to run the SPI at 50 MHz, that is more or less the standard for a particular generation of ADCs. But of course, if it can run still faster, that would be great. I can look for an ADC with a faster readout.
Thank you
P/S This is for a new board design.
In KurtE's FlexIO page at github, it seems to say the default clock rate for the FlexIO is 30MHz. And, it offers the following which seems to change the master clock for the FlexIO.
Code:
void setClockSettings(uint8_t clk_sel, uint8_t clk_pred, uint8_t clk_podf);
It seems like these arguments align with Figure 14-2. Clock tree part 1, the processor reference manual Rev 3, page 1010.
In the KurtE's FlexIOSPI there is a transaction call with a clock setting. Looking into the source code, it seems that a divider is constructed from the transaction setting and the above clock.
Now the question. In simplified terms, can a faster clock be set for the FlexIO SPI? How fast can it be? How exactly do we do that?
I would like to run the SPI at 50 MHz, that is more or less the standard for a particular generation of ADCs. But of course, if it can run still faster, that would be great. I can look for an ADC with a faster readout.
Thank you
P/S This is for a new board design.