Dogbone06
Well-known member
1170 *coff*Yup, but I have other plans for next week. Real fun should begin in April.
add ethernet to a micromod format teensy
- Thread starter mah
- Start date
holyandrei
Member
Hello, I was looking into a solution for a automotive PHY: TJA1101 and found this thread. A question I have here:
- ENET2_RX_DATA[0:1] and ENET2_TX_DATA[0:1] are mentioned in this thread as a solution, I see that the PHY that I want to use has 4 lanes: ENET2_RX_DATA[0:3] and ENET2_TX_DATA[0:3]. The speed I need to achieve is 100 mbps.
Q: are all lanes relevant to have the required speed?
PS: Sorry if I derailed the topic a bit.
- ENET2_RX_DATA[0:1] and ENET2_TX_DATA[0:1] are mentioned in this thread as a solution, I see that the PHY that I want to use has 4 lanes: ENET2_RX_DATA[0:3] and ENET2_TX_DATA[0:3]. The speed I need to achieve is 100 mbps.
Q: are all lanes relevant to have the required speed?
PS: Sorry if I derailed the topic a bit.
I pushed a new QNEthernet branch, "teensymm", that contains a driver for the hardware Paul mentioned in this thread. I consider it still experimental until the hardware design is more decided-upon. It should just work out of the box with all the examples and any existing networking code, for those that have similar hardware.
Link: https://github.com/ssilverman/QNEthernet/tree/teensymm
One "little" detail is that sometimes it doesn't work (and also freezes). A power cycle may help, but maybe not. I don't understand why yet. I suspect something to do with MDIO, as a first guess. My second guess is something to do with the PHY reset or even the reset circuit. Or, is there a brownout? (I haven't measured anything yet.)
Link: https://github.com/ssilverman/QNEthernet/tree/teensymm
One "little" detail is that sometimes it doesn't work (and also freezes). A power cycle may help, but maybe not. I don't understand why yet. I suspect something to do with MDIO, as a first guess. My second guess is something to do with the PHY reset or even the reset circuit. Or, is there a brownout? (I haven't measured anything yet.)
Last edited:
PaulStoffregen
Well-known member
I have not used TJA1101, but I did get the datasheet from NXP's web page. So please keep in mind these answers are based on a quick look at the datasheet (no actual experience with TJA1101) and familiarity with Teensy's ethernet peripheral (based on experience) and ethernet PHY connections in general.
100 Mbit ethernet PHY chips use 2 different connections, call MII and RMII. They are functionally the same.
MII clocks at 25 MHz and uses 4 data signals in each direction. RMII clocks at 50 MHz and uses 2 data signals in each direction. RMII also uses fewer extra signals.
RMII uses 7 signals and 1 pin for 50 MHz clock. Most PHY chips can either create the 50 MHz clock (usually uses a 25 MHz crystal) or configure their clock pin as an input. On MicroMod and Teensy 4.1, the main processor creates the 50 MHz, so you need to configure the PHY chip to receive the clock. Usually this is done by connecting resistors to certain pins, which the PHY chip uses at startup to configure itself.
PHY chips also have 2 pins (MDIO, MDC) for configuration and status, like checking whether the link is up. Usually use of the MDIO config is optional. Almost all PHY chips alllow configuring all the important features using resistors. As you read the datasheet, you'll find both ways documented, and usually the MIDO config offers a lot of extra non-essential stuff.
When you first get started with a new PHY chip, best to simply get it working first with resistor-only config. I believe the info you need is on page 23. You would want to configure for "RMII mode (50 MHz input on REF_CLK)"