wwatson
Well-known member
While working on a driver for the RA8889 10.1" display from Buydisplay that @Rezo brought to my attention, I discovered that there was a way to improve the performance of both RA8876 and RA8889 buy changing some clock settings:
This gives an ~200ms speed improvement. I used the piptest.ino sketch to monitor the loop cycle time. In normal speed mode the loop cycle time is ~730ms and in fast speed mode the loop cycle time is ~530ms. I tested with the 8080 parallel i/f only as I don't have a SPI display setup right now. I might also apply to the SPI version as well. Here is the link to the TeensyRA8876-8080 repo. TeensyRA8876-common repo was not altered. The settings should be safe within the given specs:
Back to the RA8889 . It's not exactly the same as the RA8876 but close
Code:
#ifdef USE_FAST_CLOCK_MODE
#define OSC_FREQ 10 // OSC clock frequency, unit: MHz.
#define DRAM_FREQ 166 // 120 // SDRAM clock frequency, unit: MHz. RA8876
#define CORE_FREQ 130 // 120 // Core (system) clock frequency, unit: MHz.
#define SCAN_FREQ 35 // 50 // Panel Scan clock frequency, unit: MHz.
#else
#define OSC_FREQ 10 // OSC clock frequency, unit: MHz.
#define DRAM_FREQ 120 // 120 // SDRAM clock frequency, unit: MHz. RA8876
#define CORE_FREQ 120 // 120 // Core (system) clock frequency, unit: MHz.
#define SCAN_FREQ 50 // 50 // Panel Scan clock frequency, unit: MHz.
#endif
Code:
/*==== [SW_(1)] PLL =====*/
// Crystal resonator for RA8876, suggested 10MHz
// SDRAM access clock,suggested 50~160MHz
// RA8876 system core clock, suggested 50~130MHz
// TFT driving clock PCLK, refer to LCD SPEC specified PCLK frequency requirements
// DRAM_FREQ >= CORE_FREQ
// CORE_FREQ >= 2 * SCAN_FREQ
Back to the RA8889 . It's not exactly the same as the RA8876 but close