XBAR pins 7, 8, 36 not working as UART CTS.

lrtjosh

Active member
Hi,

I have a setup with multiple Teensy 4.1's connected together using various serial busses, including the use of CTS + RTS pins on every connection. All of the CTS pins are using XBAR pins, and I am using low/high inverters on the RTS->CTS paths to counteract the known IMXRT1062 hardware CTS reverse polarity issue as confirmed in this thread.

Most of these connections work beautifully, with the CTS pins causing TX to pause until the receiver is ready for more bits.

HOWEVER, after chasing my tail for many hours it appears that three of the XBAR pins don't work as CTS. I have only been able to test the XBAR pins up to 37 (higher pins are not soldered on my boards), but here are my test results:

Code:
Pin 0:    ok        (ALT XBAR)
Pin 1:    ok        (XBAR)
Pin 2:    ok        (XBAR)
Pin 3:    ok        (XBAR)
Pin 4:    ok        (XBAR)
Pin 5:    ok        (XBAR)
Pin 7:    FAILED    (XBAR)
Pin 8:    FAILED    (XBAR)
Pin 30:    ok        (XBAR)
Pin 31:    ok        (XBAR)
Pin 32:    ok        (XBAR)
Pin 33:    ok        (XBAR)
Pin 36:    FAILED    (ALT XBAR)
Pin 37:    ok        (ALT XBAR)

I got my list of XBAR pins from the PJRC page about Teensy Serial. I see in HardwareSerial.cpp that the three failing CTS pins have something in common - in the section starting from line #720 const pin_to_xbar_info_t PROGMEM pin_to_xbar_info[] they specify nullptr on the select_input_register field.

Interestingly I notice that pin 1 also uses nullptr in the same field but does work as a CTS pin. That's about the point where I reach the end of my understanding, as I'm not well across the lower level IMXRT stuff.

Any ideas would be much appreciated!

Cheers,

Josh
 
Last edited:
Looks like, maybe some of the pins, actually do have INPUT select, which did not show up when I searched for them back then.
Not sure if the Rev3 manual updated some of this? Or I just missed them.

Try changing the table in HardwareSerial.cpp like:
Code:
extern const pin_to_xbar_info_t PROGMEM pin_to_xbar_info[] __attribute__((weak)) = {
    {0,  17, 1, &IOMUXC_XBAR1_IN17_SELECT_INPUT, 0x1},
    {1,  16, 1, nullptr, 0},
    {2,   6, 3, &IOMUXC_XBAR1_IN06_SELECT_INPUT, 0x0},
    {3,   7, 3, &IOMUXC_XBAR1_IN07_SELECT_INPUT, 0x0},
    {4,   8, 3, &IOMUXC_XBAR1_IN08_SELECT_INPUT, 0x0},
    {5,  17, 3, &IOMUXC_XBAR1_IN17_SELECT_INPUT, 0x0},
    {7,  15, 1, &IOMUXC_XBAR1_IN15_SELECT_INPUT, 0x1},
    {8,  14, 1, &IOMUXC_XBAR1_IN14_SELECT_INPUT, 0x1},
    {30, 23, 1, &IOMUXC_XBAR1_IN23_SELECT_INPUT, 0x0},
    {31, 22, 1, &IOMUXC_XBAR1_IN22_SELECT_INPUT, 0x0},
    {32, 10, 1, nullptr, 0},
    {33,  9, 3, &IOMUXC_XBAR1_IN09_SELECT_INPUT, 0x0},

#ifdef ARDUINO_TEENSY41
    {36, 16, 1, &IOMUXC_XBAR1_IN16_SELECT_INPUT, 0x1},
    {37, 17, 1, &IOMUXC_XBAR1_IN17_SELECT_INPUT, 0x3},
    {42,  7, 3, &IOMUXC_XBAR1_IN07_SELECT_INPUT, 0x1},
    {43,  6, 3, &IOMUXC_XBAR1_IN06_SELECT_INPUT, 0x1},
    {44,  5, 3, &IOMUXC_XBAR1_IN05_SELECT_INPUT, 0x1},
    {45,  4, 3, &IOMUXC_XBAR1_IN04_SELECT_INPUT, 0x1},
    {46,  9, 3, &IOMUXC_XBAR1_IN09_SELECT_INPUT, 0x1},
    {47,  8, 3, &IOMUXC_XBAR1_IN08_SELECT_INPUT, 0x1}
#elif defined(ARDUINO_TEENSY_MICROMOD)
    {34,  7, 3, &IOMUXC_XBAR1_IN07_SELECT_INPUT, 0x1},
    {35,  6, 3, &IOMUXC_XBAR1_IN06_SELECT_INPUT, 0x1},
    {36,  5, 3, &IOMUXC_XBAR1_IN05_SELECT_INPUT, 0x1},
    {37,  4, 3, &IOMUXC_XBAR1_IN04_SELECT_INPUT, 0x1},
    {38,  8, 3, &IOMUXC_XBAR1_IN08_SELECT_INPUT, 0x1},
    {39,  9, 3, &IOMUXC_XBAR1_IN09_SELECT_INPUT, 0x1}
#else   
    {34,  7, 3, &IOMUXC_XBAR1_IN07_SELECT_INPUT, 0x1},
    {35,  6, 3, &IOMUXC_XBAR1_IN06_SELECT_INPUT, 0x1},
    {36,  5, 3, &IOMUXC_XBAR1_IN05_SELECT_INPUT, 0x1},
    {37,  4, 3, &IOMUXC_XBAR1_IN04_SELECT_INPUT, 0x1},
    {38,  9, 3, &IOMUXC_XBAR1_IN09_SELECT_INPUT, 0x1},
    {39,  8, 3, &IOMUXC_XBAR1_IN08_SELECT_INPUT, 0x1}
#endif
};

And if it works, I can issue a Pull Request with the changes.


Thanks and Sorry...
 
@KurtE you absolute legend. That fixes all three pins.

A PR seems in order! Let me know if there's anything I can do to help, not that I know what anything in that table means beyond the first column 🤣.
 
A follow-up on something really strange I've since discovered.

I have a custom Teensy 4.1 PCB that uses an additional 32 pins for a total of 87. The extra pins have been working perfectly as basic GPIO in/out pins, using only with pinMode(), digitalWrite() and digitalRead().

Curiously, I discovered that if I make a call to pinMode(INPUT, 80) before trying to attach pin 43 (which is GPIO_SD_B0_02) as a CTS pin to a serial buss, the attach fails. Pin 80 on my board is GPIO_SD_B1_05, and all my pins <= 55 are the standard T4.1 configuration. I haven't tested every pin exhaustively, but it appears it's might only be this pin (GPIO_SD_B1_05) that causes the interference. There are lots of others that don't cause a problem when handled the same way.

I could be way off on this, but looking deeper into attachCts(uint8_t pin) (which lives in HardwareSerial.cpp), the function is returning false because the pin_to_xbar_info[] table has become corrupted/garbled after the call to pinMode(INPUT, 80). Control flows through to the end of the function without matching a pin, despite pin 43 (my CTS pin) being right there in the source code. I used Serial.printf() to dump the values of pin_to_xbar_info[].pin during the for() loop on line 389, in two different scenarios:

Scenario 1: I have just called pinMode(INPUT, various_pins_other_than_pin_80):
Code:
0, 1, 2, 3, 4, 5, 7, 8, 30, 31, 32, 33, 36, 37, 42, 43
That's what I expected to see. The loop finds the hard coded XBAR PIN numbers until it matches at 43 and returns true. Even if I call pinMode with another custom pin such as 81 etc, it's still ok and I get the same results.

Scenario 2: I have just called pinMode(INPUT, 80):
Code:
0,1, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17
The values in the table have become wonky.

To eliminate any other variables or memory issues, I have reduced down to just this proof-of-concept sketch:

Code:
#include <Arduino.h>

const int inputPin = 80;

void setup() {

  Serial.begin(0);
  while (!Serial);

  Serial.printf("Setting pin %u INPUT.\n", inputPin);
  pinMode(inputPin, INPUT);

  Serial.printf("Setting up Serial8.\n");

  Serial8.begin(2000000);
  if (Serial8.attachCts(43)) {
    Serial.printf("CTS attached to pin 43.\n");
  } else {
    Serial.printf("*** CTS pin 43 NOT ATTACHED.\n");
  }
  if (Serial8.attachRts(42)) {
    Serial.printf("RTS attached to pin 42.\n");
  } else {
    Serial.printf("*** RTS pin 43 NOT ATTACHED.\n");
  }

}

void loop() {
}

The result gives *** CTS pin 43 NOT ATTACHED, as attachCts() is returning false as described above.

I don't have much understanding of XBAR, but I also wouldn't expect this weird memory behaviour even if I was violating some kind of disallowed XBAR pin combinations.

Any thoughts? Thanks in advance!

- Josh

ps: Sorry for all the edits, I was tired.
 
Scenario 1: I have just called pinMode(INPUT, various_pins_other_than_pin_80):
Code:
0, 1, 2, 3, 4, 5, 7, 8, 30, 31, 32, 33, 36, 37, 42, 43
That's what I expected to see. The loop finds the hard coded XBAR PIN numbers until it matches at 43 and returns true. Even if I call pinMode with another custom pin such as 81 etc, it's still ok and I get the same results.

Scenario 2: I have just called pinMode(INPUT, 80):
Not sure what pinMode(INPUT, 80) would do?
I assume this is a typo? Should be pinMode(80, INPUT);
Likewise for the one above it.

Note: INPUT is #define of 0...

Sorry not sure what the MODE of 80 will do...
 
We would need to see what your digital_pin_to_info_PGM[] struct looks like (in digital.c) to see how the extra pins are being handled, sounds like they are not correctly implemented. Everything that pinMode() touches comes from that struct.
 
OK I've managed to demonstrate the weirdness in a much clearer way, but first I've simplified everything right down to just a fresh copy of the Teensy core repo (master branch), modified with one extra pin to eliminate most of the potential nonsense from my side. A reminder I'm using T4.1 only.

Relevant modified sections in core_pins.h:

Code:
#elif defined(__IMXRT1062__) && defined(ARDUINO_TEENSY41)

#define CORE_NUM_TOTAL_PINS    56
#define CORE_NUM_DIGITAL    56
#define CORE_NUM_INTERRUPT    56
#define CORE_NUM_ANALOG        18
#define CORE_NUM_PWM        31

#define CORE_PIN0_BIT        3
#define CORE_PIN1_BIT        2
#define CORE_PIN2_BIT        4
#define CORE_PIN3_BIT        5
#define CORE_PIN4_BIT        6
#define CORE_PIN5_BIT        8
#define CORE_PIN6_BIT        10
#define CORE_PIN7_BIT        17
#define CORE_PIN8_BIT        16
#define CORE_PIN9_BIT        11
#define CORE_PIN10_BIT        0
#define CORE_PIN11_BIT        2
#define CORE_PIN12_BIT        1
#define CORE_PIN13_BIT        3
#define CORE_PIN14_BIT        18
#define CORE_PIN15_BIT        19
#define CORE_PIN16_BIT        23
#define CORE_PIN17_BIT        22
#define CORE_PIN18_BIT        17
#define CORE_PIN19_BIT        16
#define CORE_PIN20_BIT        26
#define CORE_PIN21_BIT        27
#define CORE_PIN22_BIT        24
#define CORE_PIN23_BIT        25
#define CORE_PIN24_BIT        12
#define CORE_PIN25_BIT        13
#define CORE_PIN26_BIT        30
#define CORE_PIN27_BIT        31
#define CORE_PIN28_BIT        18
#define CORE_PIN29_BIT        31
#define CORE_PIN30_BIT        23
#define CORE_PIN31_BIT        22
#define CORE_PIN32_BIT        12
#define CORE_PIN33_BIT        7
#define CORE_PIN34_BIT        29
#define CORE_PIN35_BIT        28
#define CORE_PIN36_BIT        18
#define CORE_PIN37_BIT        19
#define CORE_PIN38_BIT        28
#define CORE_PIN39_BIT        29
#define CORE_PIN40_BIT        20
#define CORE_PIN41_BIT        21
#define CORE_PIN42_BIT        15
#define CORE_PIN43_BIT        14
#define CORE_PIN44_BIT        13
#define CORE_PIN45_BIT        12
#define CORE_PIN46_BIT        17
#define CORE_PIN47_BIT        16
#define CORE_PIN48_BIT        24
#define CORE_PIN49_BIT        27
#define CORE_PIN50_BIT        28
#define CORE_PIN51_BIT        22
#define CORE_PIN52_BIT        26
#define CORE_PIN53_BIT        25
#define CORE_PIN54_BIT        29
#define CORE_PIN55_BIT        5

#define CORE_PIN0_BITMASK    (1<<(CORE_PIN0_BIT))
#define CORE_PIN1_BITMASK    (1<<(CORE_PIN1_BIT))
#define CORE_PIN2_BITMASK    (1<<(CORE_PIN2_BIT))
#define CORE_PIN3_BITMASK    (1<<(CORE_PIN3_BIT))
#define CORE_PIN4_BITMASK    (1<<(CORE_PIN4_BIT))
#define CORE_PIN5_BITMASK    (1<<(CORE_PIN5_BIT))
#define CORE_PIN6_BITMASK    (1<<(CORE_PIN6_BIT))
#define CORE_PIN7_BITMASK    (1<<(CORE_PIN7_BIT))
#define CORE_PIN8_BITMASK    (1<<(CORE_PIN8_BIT))
#define CORE_PIN9_BITMASK    (1<<(CORE_PIN9_BIT))
#define CORE_PIN10_BITMASK    (1<<(CORE_PIN10_BIT))
#define CORE_PIN11_BITMASK    (1<<(CORE_PIN11_BIT))
#define CORE_PIN12_BITMASK    (1<<(CORE_PIN12_BIT))
#define CORE_PIN13_BITMASK    (1<<(CORE_PIN13_BIT))
#define CORE_PIN14_BITMASK    (1<<(CORE_PIN14_BIT))
#define CORE_PIN15_BITMASK    (1<<(CORE_PIN15_BIT))
#define CORE_PIN16_BITMASK    (1<<(CORE_PIN16_BIT))
#define CORE_PIN17_BITMASK    (1<<(CORE_PIN17_BIT))
#define CORE_PIN18_BITMASK    (1<<(CORE_PIN18_BIT))
#define CORE_PIN19_BITMASK    (1<<(CORE_PIN19_BIT))
#define CORE_PIN20_BITMASK    (1<<(CORE_PIN20_BIT))
#define CORE_PIN21_BITMASK    (1<<(CORE_PIN21_BIT))
#define CORE_PIN22_BITMASK    (1<<(CORE_PIN22_BIT))
#define CORE_PIN23_BITMASK    (1<<(CORE_PIN23_BIT))
#define CORE_PIN24_BITMASK    (1<<(CORE_PIN24_BIT))
#define CORE_PIN25_BITMASK    (1<<(CORE_PIN25_BIT))
#define CORE_PIN26_BITMASK    (1<<(CORE_PIN26_BIT))
#define CORE_PIN27_BITMASK    (1<<(CORE_PIN27_BIT))
#define CORE_PIN28_BITMASK    (1<<(CORE_PIN28_BIT))
#define CORE_PIN29_BITMASK    (1<<(CORE_PIN29_BIT))
#define CORE_PIN30_BITMASK    (1<<(CORE_PIN30_BIT))
#define CORE_PIN31_BITMASK    (1<<(CORE_PIN31_BIT))
#define CORE_PIN32_BITMASK    (1<<(CORE_PIN32_BIT))
#define CORE_PIN33_BITMASK    (1<<(CORE_PIN33_BIT))
#define CORE_PIN34_BITMASK    (1<<(CORE_PIN34_BIT))
#define CORE_PIN35_BITMASK    (1<<(CORE_PIN35_BIT))
#define CORE_PIN36_BITMASK    (1<<(CORE_PIN36_BIT))
#define CORE_PIN37_BITMASK    (1<<(CORE_PIN37_BIT))
#define CORE_PIN38_BITMASK    (1<<(CORE_PIN38_BIT))
#define CORE_PIN39_BITMASK    (1<<(CORE_PIN39_BIT))
#define CORE_PIN40_BITMASK    (1<<(CORE_PIN40_BIT))
#define CORE_PIN41_BITMASK    (1<<(CORE_PIN41_BIT))
#define CORE_PIN42_BITMASK    (1<<(CORE_PIN42_BIT))
#define CORE_PIN43_BITMASK    (1<<(CORE_PIN43_BIT))
#define CORE_PIN44_BITMASK    (1<<(CORE_PIN44_BIT))
#define CORE_PIN45_BITMASK    (1<<(CORE_PIN45_BIT))
#define CORE_PIN46_BITMASK    (1<<(CORE_PIN46_BIT))
#define CORE_PIN47_BITMASK    (1<<(CORE_PIN47_BIT))
#define CORE_PIN48_BITMASK    (1<<(CORE_PIN48_BIT))
#define CORE_PIN49_BITMASK    (1<<(CORE_PIN49_BIT))
#define CORE_PIN50_BITMASK    (1<<(CORE_PIN50_BIT))
#define CORE_PIN51_BITMASK    (1<<(CORE_PIN51_BIT))
#define CORE_PIN52_BITMASK    (1<<(CORE_PIN52_BIT))
#define CORE_PIN53_BITMASK    (1<<(CORE_PIN53_BIT))
#define CORE_PIN54_BITMASK    (1<<(CORE_PIN54_BIT))
#define CORE_PIN55_BITMASK    (1<<(CORE_PIN55_BIT))

// Fast GPIO
#define CORE_PIN0_PORTREG    GPIO6_DR
#define CORE_PIN1_PORTREG    GPIO6_DR
#define CORE_PIN2_PORTREG    GPIO9_DR
#define CORE_PIN3_PORTREG    GPIO9_DR
#define CORE_PIN4_PORTREG    GPIO9_DR
#define CORE_PIN5_PORTREG    GPIO9_DR
#define CORE_PIN6_PORTREG    GPIO7_DR
#define CORE_PIN7_PORTREG    GPIO7_DR
#define CORE_PIN8_PORTREG    GPIO7_DR
#define CORE_PIN9_PORTREG    GPIO7_DR
#define CORE_PIN10_PORTREG    GPIO7_DR
#define CORE_PIN11_PORTREG    GPIO7_DR
#define CORE_PIN12_PORTREG    GPIO7_DR
#define CORE_PIN13_PORTREG    GPIO7_DR
#define CORE_PIN14_PORTREG    GPIO6_DR
#define CORE_PIN15_PORTREG    GPIO6_DR
#define CORE_PIN16_PORTREG    GPIO6_DR
#define CORE_PIN17_PORTREG    GPIO6_DR
#define CORE_PIN18_PORTREG    GPIO6_DR
#define CORE_PIN19_PORTREG    GPIO6_DR
#define CORE_PIN20_PORTREG    GPIO6_DR
#define CORE_PIN21_PORTREG    GPIO6_DR
#define CORE_PIN22_PORTREG    GPIO6_DR
#define CORE_PIN23_PORTREG    GPIO6_DR
#define CORE_PIN24_PORTREG    GPIO6_DR
#define CORE_PIN25_PORTREG    GPIO6_DR
#define CORE_PIN26_PORTREG    GPIO6_DR
#define CORE_PIN27_PORTREG    GPIO6_DR
#define CORE_PIN28_PORTREG    GPIO8_DR
#define CORE_PIN29_PORTREG    GPIO9_DR
#define CORE_PIN30_PORTREG    GPIO8_DR
#define CORE_PIN31_PORTREG    GPIO8_DR
#define CORE_PIN32_PORTREG    GPIO7_DR
#define CORE_PIN33_PORTREG    GPIO9_DR
#define CORE_PIN34_PORTREG    GPIO7_DR
#define CORE_PIN35_PORTREG    GPIO7_DR
#define CORE_PIN36_PORTREG    GPIO7_DR
#define CORE_PIN37_PORTREG    GPIO7_DR
#define CORE_PIN38_PORTREG    GPIO6_DR
#define CORE_PIN39_PORTREG    GPIO6_DR
#define CORE_PIN40_PORTREG    GPIO6_DR
#define CORE_PIN41_PORTREG    GPIO6_DR
#define CORE_PIN42_PORTREG    GPIO8_DR
#define CORE_PIN43_PORTREG    GPIO8_DR
#define CORE_PIN44_PORTREG    GPIO8_DR
#define CORE_PIN45_PORTREG    GPIO8_DR
#define CORE_PIN46_PORTREG    GPIO8_DR
#define CORE_PIN47_PORTREG    GPIO8_DR
#define CORE_PIN48_PORTREG    GPIO9_DR
#define CORE_PIN49_PORTREG    GPIO9_DR
#define CORE_PIN50_PORTREG    GPIO9_DR
#define CORE_PIN51_PORTREG    GPIO9_DR
#define CORE_PIN52_PORTREG    GPIO9_DR
#define CORE_PIN53_PORTREG    GPIO9_DR
#define CORE_PIN54_PORTREG    GPIO9_DR
#define CORE_PIN55_PORTREG    GPIO8_DR

#define CORE_PIN0_PORTSET    GPIO6_DR_SET
#define CORE_PIN1_PORTSET    GPIO6_DR_SET
#define CORE_PIN2_PORTSET    GPIO9_DR_SET
#define CORE_PIN3_PORTSET    GPIO9_DR_SET
#define CORE_PIN4_PORTSET    GPIO9_DR_SET
#define CORE_PIN5_PORTSET    GPIO9_DR_SET
#define CORE_PIN6_PORTSET    GPIO7_DR_SET
#define CORE_PIN7_PORTSET    GPIO7_DR_SET
#define CORE_PIN8_PORTSET    GPIO7_DR_SET
#define CORE_PIN9_PORTSET    GPIO7_DR_SET
#define CORE_PIN10_PORTSET    GPIO7_DR_SET
#define CORE_PIN11_PORTSET    GPIO7_DR_SET
#define CORE_PIN12_PORTSET    GPIO7_DR_SET
#define CORE_PIN13_PORTSET    GPIO7_DR_SET
#define CORE_PIN14_PORTSET    GPIO6_DR_SET
#define CORE_PIN15_PORTSET    GPIO6_DR_SET
#define CORE_PIN16_PORTSET    GPIO6_DR_SET
#define CORE_PIN17_PORTSET    GPIO6_DR_SET
#define CORE_PIN18_PORTSET    GPIO6_DR_SET
#define CORE_PIN19_PORTSET    GPIO6_DR_SET
#define CORE_PIN20_PORTSET    GPIO6_DR_SET
#define CORE_PIN21_PORTSET    GPIO6_DR_SET
#define CORE_PIN22_PORTSET    GPIO6_DR_SET
#define CORE_PIN23_PORTSET    GPIO6_DR_SET
#define CORE_PIN24_PORTSET    GPIO6_DR_SET
#define CORE_PIN25_PORTSET    GPIO6_DR_SET
#define CORE_PIN26_PORTSET    GPIO6_DR_SET
#define CORE_PIN27_PORTSET    GPIO6_DR_SET
#define CORE_PIN28_PORTSET    GPIO8_DR_SET
#define CORE_PIN29_PORTSET    GPIO9_DR_SET
#define CORE_PIN30_PORTSET    GPIO8_DR_SET
#define CORE_PIN31_PORTSET    GPIO8_DR_SET
#define CORE_PIN32_PORTSET    GPIO7_DR_SET
#define CORE_PIN33_PORTSET    GPIO9_DR_SET
#define CORE_PIN34_PORTSET    GPIO7_DR_SET
#define CORE_PIN35_PORTSET    GPIO7_DR_SET
#define CORE_PIN36_PORTSET    GPIO7_DR_SET
#define CORE_PIN37_PORTSET    GPIO7_DR_SET
#define CORE_PIN38_PORTSET    GPIO6_DR_SET
#define CORE_PIN39_PORTSET    GPIO6_DR_SET
#define CORE_PIN40_PORTSET    GPIO6_DR_SET
#define CORE_PIN41_PORTSET    GPIO6_DR_SET
#define CORE_PIN42_PORTSET    GPIO8_DR_SET
#define CORE_PIN43_PORTSET    GPIO8_DR_SET
#define CORE_PIN44_PORTSET    GPIO8_DR_SET
#define CORE_PIN45_PORTSET    GPIO8_DR_SET
#define CORE_PIN46_PORTSET    GPIO8_DR_SET
#define CORE_PIN47_PORTSET    GPIO8_DR_SET
#define CORE_PIN48_PORTSET    GPIO9_DR_SET
#define CORE_PIN49_PORTSET    GPIO9_DR_SET
#define CORE_PIN50_PORTSET    GPIO9_DR_SET
#define CORE_PIN51_PORTSET    GPIO9_DR_SET
#define CORE_PIN52_PORTSET    GPIO9_DR_SET
#define CORE_PIN53_PORTSET    GPIO9_DR_SET
#define CORE_PIN54_PORTSET    GPIO9_DR_SET
#define CORE_PIN55_PORTSET    GPIO8_DR_SET

#define CORE_PIN0_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN1_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN2_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN3_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN4_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN5_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN6_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN7_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN8_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN9_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN10_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN11_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN12_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN13_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN14_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN15_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN16_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN17_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN18_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN19_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN20_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN21_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN22_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN23_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN24_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN25_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN26_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN27_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN28_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN29_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN30_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN31_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN32_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN33_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN34_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN35_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN36_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN37_PORTCLEAR    GPIO7_DR_CLEAR
#define CORE_PIN38_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN39_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN40_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN41_PORTCLEAR    GPIO6_DR_CLEAR
#define CORE_PIN42_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN43_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN44_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN45_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN46_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN47_PORTCLEAR    GPIO8_DR_CLEAR
#define CORE_PIN48_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN49_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN50_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN51_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN52_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN53_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN54_PORTCLEAR    GPIO9_DR_CLEAR
#define CORE_PIN55_PORTCLEAR    GPIO8_DR_CLEAR

#define CORE_PIN0_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN1_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN2_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN3_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN4_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN5_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN6_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN7_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN8_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN9_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN10_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN11_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN12_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN13_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN14_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN15_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN16_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN17_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN18_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN19_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN20_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN21_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN22_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN23_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN24_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN25_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN26_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN27_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN28_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN29_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN30_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN31_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN32_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN33_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN34_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN35_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN36_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN37_PORTTOGGLE    GPIO7_DR_TOGGLE
#define CORE_PIN38_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN39_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN40_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN41_PORTTOGGLE    GPIO6_DR_TOGGLE
#define CORE_PIN42_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN43_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN44_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN45_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN46_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN47_PORTTOGGLE    GPIO8_DR_TOGGLE
#define CORE_PIN48_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN49_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN50_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN51_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN52_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN53_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN54_PORTTOGGLE    GPIO9_DR_TOGGLE
#define CORE_PIN55_PORTTOGGLE    GPIO8_DR_TOGGLE

#define CORE_PIN0_DDRREG    GPIO6_GDIR
#define CORE_PIN1_DDRREG    GPIO6_GDIR
#define CORE_PIN2_DDRREG    GPIO9_GDIR
#define CORE_PIN3_DDRREG    GPIO9_GDIR
#define CORE_PIN4_DDRREG    GPIO9_GDIR
#define CORE_PIN5_DDRREG    GPIO9_GDIR
#define CORE_PIN6_DDRREG    GPIO7_GDIR
#define CORE_PIN7_DDRREG    GPIO7_GDIR
#define CORE_PIN8_DDRREG    GPIO7_GDIR
#define CORE_PIN9_DDRREG    GPIO7_GDIR
#define CORE_PIN10_DDRREG    GPIO7_GDIR
#define CORE_PIN11_DDRREG    GPIO7_GDIR
#define CORE_PIN12_DDRREG    GPIO7_GDIR
#define CORE_PIN13_DDRREG    GPIO7_GDIR
#define CORE_PIN14_DDRREG    GPIO6_GDIR
#define CORE_PIN15_DDRREG    GPIO6_GDIR
#define CORE_PIN16_DDRREG    GPIO6_GDIR
#define CORE_PIN17_DDRREG    GPIO6_GDIR
#define CORE_PIN18_DDRREG    GPIO6_GDIR
#define CORE_PIN19_DDRREG    GPIO6_GDIR
#define CORE_PIN20_DDRREG    GPIO6_GDIR
#define CORE_PIN21_DDRREG    GPIO6_GDIR
#define CORE_PIN22_DDRREG    GPIO6_GDIR
#define CORE_PIN23_DDRREG    GPIO6_GDIR
#define CORE_PIN24_DDRREG    GPIO6_GDIR
#define CORE_PIN25_DDRREG    GPIO6_GDIR
#define CORE_PIN26_DDRREG    GPIO6_GDIR
#define CORE_PIN27_DDRREG    GPIO6_GDIR
#define CORE_PIN28_DDRREG    GPIO8_GDIR
#define CORE_PIN29_DDRREG    GPIO9_GDIR
#define CORE_PIN30_DDRREG    GPIO8_GDIR
#define CORE_PIN31_DDRREG    GPIO8_GDIR
#define CORE_PIN32_DDRREG    GPIO7_GDIR
#define CORE_PIN33_DDRREG    GPIO9_GDIR
#define CORE_PIN34_DDRREG    GPIO7_GDIR
#define CORE_PIN35_DDRREG    GPIO7_GDIR
#define CORE_PIN36_DDRREG    GPIO7_GDIR
#define CORE_PIN37_DDRREG    GPIO7_GDIR
#define CORE_PIN38_DDRREG    GPIO6_GDIR
#define CORE_PIN39_DDRREG    GPIO6_GDIR
#define CORE_PIN40_DDRREG    GPIO6_GDIR
#define CORE_PIN41_DDRREG    GPIO6_GDIR
#define CORE_PIN42_DDRREG    GPIO8_GDIR
#define CORE_PIN43_DDRREG    GPIO8_GDIR
#define CORE_PIN44_DDRREG    GPIO8_GDIR
#define CORE_PIN45_DDRREG    GPIO8_GDIR
#define CORE_PIN46_DDRREG    GPIO8_GDIR
#define CORE_PIN47_DDRREG    GPIO8_GDIR
#define CORE_PIN48_DDRREG    GPIO9_GDIR
#define CORE_PIN49_DDRREG    GPIO9_GDIR
#define CORE_PIN50_DDRREG    GPIO9_GDIR
#define CORE_PIN51_DDRREG    GPIO9_GDIR
#define CORE_PIN52_DDRREG    GPIO9_GDIR
#define CORE_PIN53_DDRREG    GPIO9_GDIR
#define CORE_PIN54_DDRREG    GPIO9_GDIR
#define CORE_PIN55_DDRREG    GPIO8_GDIR

#define CORE_PIN0_PINREG    GPIO6_PSR
#define CORE_PIN1_PINREG    GPIO6_PSR
#define CORE_PIN2_PINREG    GPIO9_PSR
#define CORE_PIN3_PINREG    GPIO9_PSR
#define CORE_PIN4_PINREG    GPIO9_PSR
#define CORE_PIN5_PINREG    GPIO9_PSR
#define CORE_PIN6_PINREG    GPIO7_PSR
#define CORE_PIN7_PINREG    GPIO7_PSR
#define CORE_PIN8_PINREG    GPIO7_PSR
#define CORE_PIN9_PINREG    GPIO7_PSR
#define CORE_PIN10_PINREG    GPIO7_PSR
#define CORE_PIN11_PINREG    GPIO7_PSR
#define CORE_PIN12_PINREG    GPIO7_PSR
#define CORE_PIN13_PINREG    GPIO7_PSR
#define CORE_PIN14_PINREG    GPIO6_PSR
#define CORE_PIN15_PINREG    GPIO6_PSR
#define CORE_PIN16_PINREG    GPIO6_PSR
#define CORE_PIN17_PINREG    GPIO6_PSR
#define CORE_PIN18_PINREG    GPIO6_PSR
#define CORE_PIN19_PINREG    GPIO6_PSR
#define CORE_PIN20_PINREG    GPIO6_PSR
#define CORE_PIN21_PINREG    GPIO6_PSR
#define CORE_PIN22_PINREG    GPIO6_PSR
#define CORE_PIN23_PINREG    GPIO6_PSR
#define CORE_PIN24_PINREG    GPIO6_PSR
#define CORE_PIN25_PINREG    GPIO6_PSR
#define CORE_PIN26_PINREG    GPIO6_PSR
#define CORE_PIN27_PINREG    GPIO6_PSR
#define CORE_PIN28_PINREG    GPIO8_PSR
#define CORE_PIN29_PINREG    GPIO9_PSR
#define CORE_PIN30_PINREG    GPIO8_PSR
#define CORE_PIN31_PINREG    GPIO8_PSR
#define CORE_PIN32_PINREG    GPIO7_PSR
#define CORE_PIN33_PINREG    GPIO9_PSR
#define CORE_PIN34_PINREG    GPIO7_PSR
#define CORE_PIN35_PINREG    GPIO7_PSR
#define CORE_PIN36_PINREG    GPIO7_PSR
#define CORE_PIN37_PINREG    GPIO7_PSR
#define CORE_PIN38_PINREG    GPIO6_PSR
#define CORE_PIN39_PINREG    GPIO6_PSR
#define CORE_PIN40_PINREG    GPIO6_PSR
#define CORE_PIN41_PINREG    GPIO6_PSR
#define CORE_PIN42_PINREG    GPIO8_PSR
#define CORE_PIN43_PINREG    GPIO8_PSR
#define CORE_PIN44_PINREG    GPIO8_PSR
#define CORE_PIN45_PINREG    GPIO8_PSR
#define CORE_PIN46_PINREG    GPIO8_PSR
#define CORE_PIN47_PINREG    GPIO8_PSR
#define CORE_PIN48_PINREG    GPIO9_PSR
#define CORE_PIN49_PINREG    GPIO9_PSR
#define CORE_PIN50_PINREG    GPIO9_PSR
#define CORE_PIN51_PINREG    GPIO9_PSR
#define CORE_PIN52_PINREG    GPIO9_PSR
#define CORE_PIN53_PINREG    GPIO9_PSR
#define CORE_PIN54_PINREG    GPIO9_PSR
#define CORE_PIN55_PINREG    GPIO8_PSR

// mux config registers control which peripheral uses the pin
#define CORE_PIN0_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
#define CORE_PIN1_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
#define CORE_PIN2_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
#define CORE_PIN3_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
#define CORE_PIN4_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
#define CORE_PIN5_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
#define CORE_PIN6_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
#define CORE_PIN7_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
#define CORE_PIN8_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
#define CORE_PIN9_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
#define CORE_PIN10_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
#define CORE_PIN11_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
#define CORE_PIN12_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
#define CORE_PIN13_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
#define CORE_PIN14_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
#define CORE_PIN15_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
#define CORE_PIN16_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
#define CORE_PIN17_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
#define CORE_PIN18_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
#define CORE_PIN19_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
#define CORE_PIN20_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
#define CORE_PIN21_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
#define CORE_PIN22_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
#define CORE_PIN23_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
#define CORE_PIN24_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
#define CORE_PIN25_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
#define CORE_PIN26_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
#define CORE_PIN27_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
#define CORE_PIN28_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
#define CORE_PIN29_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
#define CORE_PIN30_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
#define CORE_PIN31_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
#define CORE_PIN32_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
#define CORE_PIN33_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
#define CORE_PIN34_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
#define CORE_PIN35_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
#define CORE_PIN36_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
#define CORE_PIN37_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
#define CORE_PIN38_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
#define CORE_PIN39_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
#define CORE_PIN40_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
#define CORE_PIN41_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
#define CORE_PIN42_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
#define CORE_PIN43_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
#define CORE_PIN44_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
#define CORE_PIN45_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
#define CORE_PIN46_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
#define CORE_PIN47_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
#define CORE_PIN48_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
#define CORE_PIN49_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
#define CORE_PIN50_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
#define CORE_PIN51_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
#define CORE_PIN52_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
#define CORE_PIN53_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
#define CORE_PIN54_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
#define CORE_PIN55_CONFIG    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05

// pad config registers control pullup/pulldown/keeper, drive strength, etc
#define CORE_PIN0_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
#define CORE_PIN1_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
#define CORE_PIN2_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
#define CORE_PIN3_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
#define CORE_PIN4_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
#define CORE_PIN5_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
#define CORE_PIN6_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
#define CORE_PIN7_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
#define CORE_PIN8_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
#define CORE_PIN9_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
#define CORE_PIN10_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
#define CORE_PIN11_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
#define CORE_PIN12_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
#define CORE_PIN13_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
#define CORE_PIN14_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
#define CORE_PIN15_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
#define CORE_PIN16_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
#define CORE_PIN17_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
#define CORE_PIN18_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
#define CORE_PIN19_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
#define CORE_PIN20_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
#define CORE_PIN21_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
#define CORE_PIN22_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
#define CORE_PIN23_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
#define CORE_PIN24_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
#define CORE_PIN25_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
#define CORE_PIN26_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
#define CORE_PIN27_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
#define CORE_PIN28_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
#define CORE_PIN29_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
#define CORE_PIN30_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
#define CORE_PIN31_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
#define CORE_PIN32_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
#define CORE_PIN33_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
#define CORE_PIN34_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
#define CORE_PIN35_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
#define CORE_PIN36_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
#define CORE_PIN37_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
#define CORE_PIN38_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
#define CORE_PIN39_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
#define CORE_PIN40_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
#define CORE_PIN41_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
#define CORE_PIN42_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
#define CORE_PIN43_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
#define CORE_PIN44_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
#define CORE_PIN45_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
#define CORE_PIN46_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
#define CORE_PIN47_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
#define CORE_PIN48_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
#define CORE_PIN49_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
#define CORE_PIN50_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
#define CORE_PIN51_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
#define CORE_PIN52_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
#define CORE_PIN53_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
#define CORE_PIN54_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
#define CORE_PIN55_PADCONFIG    IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05

#define CORE_LED0_PIN        13

#define CORE_ADC0_PIN        14
#define CORE_ADC1_PIN        15
#define CORE_ADC2_PIN        16
#define CORE_ADC3_PIN        17
#define CORE_ADC4_PIN        18
#define CORE_ADC5_PIN        19
#define CORE_ADC6_PIN        20
#define CORE_ADC7_PIN        21
#define CORE_ADC8_PIN        22
#define CORE_ADC9_PIN        23

#define CORE_RXD0_PIN        0
#define CORE_TXD0_PIN        1
#define CORE_RXD1_PIN        7
#define CORE_TXD1_PIN        8
#define CORE_RXD2_PIN        15
#define CORE_TXD2_PIN        14
#define CORE_RXD3_PIN        16
#define CORE_TXD3_PIN        17
#define CORE_RXD4_PIN        21
#define CORE_TXD4_PIN        20
#define CORE_RXD5_PIN        25
#define CORE_TXD5_PIN        24
#define CORE_RXD6_PIN        28
#define CORE_TXD6_PIN        29
#define CORE_RXD7_PIN        34
#define CORE_TXD7_PIN        35

#define CORE_INT0_PIN        0
#define CORE_INT1_PIN        1
#define CORE_INT2_PIN        2
#define CORE_INT3_PIN        3
#define CORE_INT4_PIN        4
#define CORE_INT5_PIN        5
#define CORE_INT6_PIN        6
#define CORE_INT7_PIN        7
#define CORE_INT8_PIN        8
#define CORE_INT9_PIN        9
#define CORE_INT10_PIN        10
#define CORE_INT11_PIN        11
#define CORE_INT12_PIN        12
#define CORE_INT13_PIN        13
#define CORE_INT14_PIN        14
#define CORE_INT15_PIN        15
#define CORE_INT16_PIN        16
#define CORE_INT17_PIN        17
#define CORE_INT18_PIN        18
#define CORE_INT19_PIN        19
#define CORE_INT20_PIN        20
#define CORE_INT21_PIN        21
#define CORE_INT22_PIN        22
#define CORE_INT23_PIN        23
#define CORE_INT24_PIN        24
#define CORE_INT25_PIN        25
#define CORE_INT26_PIN        26
#define CORE_INT27_PIN        27
#define CORE_INT28_PIN        28
#define CORE_INT29_PIN        29
#define CORE_INT30_PIN        30
#define CORE_INT31_PIN        31
#define CORE_INT32_PIN        32
#define CORE_INT33_PIN        33
#define CORE_INT34_PIN        34
#define CORE_INT35_PIN        35
#define CORE_INT36_PIN        36
#define CORE_INT37_PIN        37
#define CORE_INT38_PIN        38
#define CORE_INT39_PIN        39
#define CORE_INT40_PIN        40
#define CORE_INT41_PIN        41
#define CORE_INT42_PIN        42
#define CORE_INT43_PIN        43
#define CORE_INT44_PIN        44
#define CORE_INT45_PIN        45
#define CORE_INT46_PIN        46
#define CORE_INT47_PIN        47
#define CORE_INT48_PIN        48
#define CORE_INT49_PIN        49
#define CORE_INT50_PIN        50
#define CORE_INT51_PIN        51
#define CORE_INT52_PIN        52
#define CORE_INT53_PIN        53
#define CORE_INT54_PIN        54
#define CORE_INT55_PIN        55
#define CORE_INT_EVERY_PIN    1
Code:
static inline void digitalWriteFast(uint8_t pin, uint8_t val)
{
    if (__builtin_constant_p(pin)) {
        if (val) {
            if (pin == 0) {
                CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;
            } else if (pin == 1) {
                CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;
            } else if (pin == 2) {
                CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;
            } else if (pin == 3) {
                CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;
            } else if (pin == 4) {
                CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;
            } else if (pin == 5) {
                CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;
            } else if (pin == 6) {
                CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;
            } else if (pin == 7) {
                CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;
            } else if (pin == 8) {
                CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;
            } else if (pin == 9) {
                CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;
            } else if (pin == 10) {
                CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;
            } else if (pin == 11) {
                CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;
            } else if (pin == 12) {
                CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;
            } else if (pin == 13) {
                CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;
            } else if (pin == 14) {
                CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;
            } else if (pin == 15) {
                CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;
            } else if (pin == 16) {
                CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;
            } else if (pin == 17) {
                CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;
            } else if (pin == 18) {
                CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;
            } else if (pin == 19) {
                CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;
            } else if (pin == 20) {
                CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;
            } else if (pin == 21) {
                CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;
            } else if (pin == 22) {
                CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;
            } else if (pin == 23) {
                CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;
            } else if (pin == 24) {
                CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;
            } else if (pin == 25) {
                CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;
            } else if (pin == 26) {
                CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;
            } else if (pin == 27) {
                CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;
            } else if (pin == 28) {
                CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;
            } else if (pin == 29) {
                CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;
            } else if (pin == 30) {
                CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;
            } else if (pin == 31) {
                CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;
            } else if (pin == 32) {
                CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
            } else if (pin == 33) {
                CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
            } else if (pin == 34) {
                CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
            } else if (pin == 35) {
                CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;
            } else if (pin == 36) {
                CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;
            } else if (pin == 37) {
                CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;
            } else if (pin == 38) {
                CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
            } else if (pin == 39) {
                CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
#if CORE_NUM_DIGITAL > 40
            } else if (pin == 40) {
                CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
            } else if (pin == 41) {
                CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
            } else if (pin == 42) {
                CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
            } else if (pin == 43) {
                CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
            } else if (pin == 44) {
                CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
            } else if (pin == 45) {
                CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
#endif
#if CORE_NUM_DIGITAL > 46
            } else if (pin == 46) {
                CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
            } else if (pin == 47) {
                CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
            } else if (pin == 48) {
                CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
            } else if (pin == 49) {
                CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
            } else if (pin == 50) {
                CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
            } else if (pin == 51) {
                CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
            } else if (pin == 52) {
                CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
            } else if (pin == 53) {
                CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
            } else if (pin == 54) {
                CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
            } else if (pin == 55) {
                CORE_PIN55_PORTSET = CORE_PIN55_BITMASK;
#endif
            }
        } else {
            if (pin == 0) {
                CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
            } else if (pin == 1) {
                CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;
            } else if (pin == 2) {
                CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;
            } else if (pin == 3) {
                CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;
            } else if (pin == 4) {
                CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;
            } else if (pin == 5) {
                CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;
            } else if (pin == 6) {
                CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;
            } else if (pin == 7) {
                CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;
            } else if (pin == 8) {
                CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;
            } else if (pin == 9) {
                CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;
            } else if (pin == 10) {
                CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;
            } else if (pin == 11) {
                CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;
            } else if (pin == 12) {
                CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;
            } else if (pin == 13) {
                CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;
            } else if (pin == 14) {
                CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;
            } else if (pin == 15) {
                CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;
            } else if (pin == 16) {
                CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;
            } else if (pin == 17) {
                CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;
            } else if (pin == 18) {
                CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;
            } else if (pin == 19) {
                CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;
            } else if (pin == 20) {
                CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;
            } else if (pin == 21) {
                CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;
            } else if (pin == 22) {
                CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;
            } else if (pin == 23) {
                CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;
            } else if (pin == 24) {
                CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;
            } else if (pin == 25) {
                CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;
            } else if (pin == 26) {
                CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;
            } else if (pin == 27) {
                CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;
            } else if (pin == 28) {
                CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;
            } else if (pin == 29) {
                CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;
            } else if (pin == 30) {
                CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;
            } else if (pin == 31) {
                CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;
            } else if (pin == 32) {
                CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
            } else if (pin == 33) {
                CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
            } else if (pin == 34) {
                CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
            } else if (pin == 35) {
                CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;
            } else if (pin == 36) {
                CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;
            } else if (pin == 37) {
                CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;
            } else if (pin == 38) {
                CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
            } else if (pin == 39) {
                CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
#if CORE_NUM_DIGITAL > 40
            } else if (pin == 40) {
                CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
            } else if (pin == 41) {
                CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
            } else if (pin == 42) {
                CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
            } else if (pin == 43) {
                CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
            } else if (pin == 44) {
                CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
            } else if (pin == 45) {
                CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
#endif
#if CORE_NUM_DIGITAL > 46
            } else if (pin == 46) {
                CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
            } else if (pin == 47) {
                CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
            } else if (pin == 48) {
                CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
            } else if (pin == 49) {
                CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
            } else if (pin == 50) {
                CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
            } else if (pin == 51) {
                CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
            } else if (pin == 52) {
                CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
            } else if (pin == 53) {
                CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
            } else if (pin == 54) {
                CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
            } else if (pin == 55) {
                CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK;
#endif
            }
        }
    } else {
        if(val) *portSetRegister(pin) = digitalPinToBitMask(pin);
        else *portClearRegister(pin) = digitalPinToBitMask(pin);
    }
}

// Read the signal at a digital pin.  The pin must have previously been
// configured with pinMode() as INPUT, INPUT_PULLUP, or INPUT_PULLDOWN.
// The return value is either HIGH or LOW.
uint8_t digitalRead(uint8_t pin);
static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));
// Read the signal at a digital pin.  The pin must have previously been
// configured with pinMode() as INPUT, INPUT_PULLUP, or INPUT_PULLDOWN.  The
// return value is either HIGH or LOW.  This fast version of digitalRead()
// has minimal overhead when the pin number is a constant.
static inline uint8_t digitalReadFast(uint8_t pin)
{
    if (__builtin_constant_p(pin)) {
        if (pin == 0) {
            return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;
        } else if (pin == 1) {
            return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;
        } else if (pin == 2) {
            return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;
        } else if (pin == 3) {
            return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;
        } else if (pin == 4) {
            return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;
        } else if (pin == 5) {
            return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;
        } else if (pin == 6) {
            return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;
        } else if (pin == 7) {
            return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;
        } else if (pin == 8) {
            return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;
        } else if (pin == 9) {
            return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;
        } else if (pin == 10) {
            return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;
        } else if (pin == 11) {
            return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;
        } else if (pin == 12) {
            return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;
        } else if (pin == 13) {
            return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;
        } else if (pin == 14) {
            return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;
        } else if (pin == 15) {
            return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;
        } else if (pin == 16) {
            return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;
        } else if (pin == 17) {
            return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;
        } else if (pin == 18) {
            return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;
        } else if (pin == 19) {
            return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;
        } else if (pin == 20) {
            return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;
        } else if (pin == 21) {
            return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;
        } else if (pin == 22) {
            return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;
        } else if (pin == 23) {
            return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;
        } else if (pin == 24) {
            return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;
        } else if (pin == 25) {
            return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;
        } else if (pin == 26) {
            return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;
        } else if (pin == 27) {
            return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;
        } else if (pin == 28) {
            return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;
        } else if (pin == 29) {
            return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;
        } else if (pin == 30) {
            return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;
        } else if (pin == 31) {
            return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;
        } else if (pin == 32) {
            return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;
        } else if (pin == 33) {
            return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
        } else if (pin == 34) {
            return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
        } else if (pin == 35) {
            return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
        } else if (pin == 36) {
            return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
        } else if (pin == 37) {
            return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
        } else if (pin == 38) {
            return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
        } else if (pin == 39) {
            return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
#if CORE_NUM_DIGITAL > 40
        } else if (pin == 40) {
            return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
        } else if (pin == 41) {
            return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
        } else if (pin == 42) {
            return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
        } else if (pin == 43) {
            return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
        } else if (pin == 44) {
            return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
        } else if (pin == 45) {
            return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
#endif
#if CORE_NUM_DIGITAL > 46
        } else if (pin == 46) {
            return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
        } else if (pin == 47) {
            return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
        } else if (pin == 48) {
            return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
        } else if (pin == 49) {
            return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
        } else if (pin == 50) {
            return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
        } else if (pin == 51) {
            return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
        } else if (pin == 52) {
            return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
        } else if (pin == 53) {
            return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
        } else if (pin == 54) {
            return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
        } else if (pin == 55) {
            return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0;
#endif
        } else {
            return 0;
        }
    } else {
        return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;
    }
}

// Cause a digital pin's output to change state.  If it was HIGH,
// the pin outputs LOW, and if it was LOW the pin outputs HIGH.  The
// pin must have been configured to OUTPUT mode with pinMode().
void digitalToggle(uint8_t pin);
static inline void digitalToggleFast(uint8_t pin) __attribute__((always_inline, unused));
// Cause a digital pin's output to change state.  This fast version
// of digitalToggle() has minimal overhead when the pin number is a
// constant.  Without additional delay, successive digitalToggleFast()
// can cause the pin to oscillate too quickly for many applications.
static inline void digitalToggleFast(uint8_t pin)
{
    if (__builtin_constant_p(pin)) {
        if (pin == 0) {
            CORE_PIN0_PORTTOGGLE = CORE_PIN0_BITMASK;
        } else if (pin == 1) {
            CORE_PIN1_PORTTOGGLE = CORE_PIN1_BITMASK;
        } else if (pin == 2) {
            CORE_PIN2_PORTTOGGLE = CORE_PIN2_BITMASK;
        } else if (pin == 3) {
            CORE_PIN3_PORTTOGGLE = CORE_PIN3_BITMASK;
        } else if (pin == 4) {
            CORE_PIN4_PORTTOGGLE = CORE_PIN4_BITMASK;
        } else if (pin == 5) {
            CORE_PIN5_PORTTOGGLE = CORE_PIN5_BITMASK;
        } else if (pin == 6) {
            CORE_PIN6_PORTTOGGLE = CORE_PIN6_BITMASK;
        } else if (pin == 7) {
            CORE_PIN7_PORTTOGGLE = CORE_PIN7_BITMASK;
        } else if (pin == 8) {
            CORE_PIN8_PORTTOGGLE = CORE_PIN8_BITMASK;
        } else if (pin == 9) {
            CORE_PIN9_PORTTOGGLE = CORE_PIN9_BITMASK;
        } else if (pin == 10) {
            CORE_PIN10_PORTTOGGLE = CORE_PIN10_BITMASK;
        } else if (pin == 11) {
            CORE_PIN11_PORTTOGGLE = CORE_PIN11_BITMASK;
        } else if (pin == 12) {
            CORE_PIN12_PORTTOGGLE = CORE_PIN12_BITMASK;
        } else if (pin == 13) {
            CORE_PIN13_PORTTOGGLE = CORE_PIN13_BITMASK;
        } else if (pin == 14) {
            CORE_PIN14_PORTTOGGLE = CORE_PIN14_BITMASK;
        } else if (pin == 15) {
            CORE_PIN15_PORTTOGGLE = CORE_PIN15_BITMASK;
        } else if (pin == 16) {
            CORE_PIN16_PORTTOGGLE = CORE_PIN16_BITMASK;
        } else if (pin == 17) {
            CORE_PIN17_PORTTOGGLE = CORE_PIN17_BITMASK;
        } else if (pin == 18) {
            CORE_PIN18_PORTTOGGLE = CORE_PIN18_BITMASK;
        } else if (pin == 19) {
            CORE_PIN19_PORTTOGGLE = CORE_PIN19_BITMASK;
        } else if (pin == 20) {
            CORE_PIN20_PORTTOGGLE = CORE_PIN20_BITMASK;
        } else if (pin == 21) {
            CORE_PIN21_PORTTOGGLE = CORE_PIN21_BITMASK;
        } else if (pin == 22) {
            CORE_PIN22_PORTTOGGLE = CORE_PIN22_BITMASK;
        } else if (pin == 23) {
            CORE_PIN23_PORTTOGGLE = CORE_PIN23_BITMASK;
        } else if (pin == 24) {
            CORE_PIN24_PORTTOGGLE = CORE_PIN24_BITMASK;
        } else if (pin == 25) {
            CORE_PIN25_PORTTOGGLE = CORE_PIN25_BITMASK;
        } else if (pin == 26) {
            CORE_PIN26_PORTTOGGLE = CORE_PIN26_BITMASK;
        } else if (pin == 27) {
            CORE_PIN27_PORTTOGGLE = CORE_PIN27_BITMASK;
        } else if (pin == 28) {
            CORE_PIN28_PORTTOGGLE = CORE_PIN28_BITMASK;
        } else if (pin == 29) {
            CORE_PIN29_PORTTOGGLE = CORE_PIN29_BITMASK;
        } else if (pin == 30) {
            CORE_PIN30_PORTTOGGLE = CORE_PIN30_BITMASK;
        } else if (pin == 31) {
            CORE_PIN31_PORTTOGGLE = CORE_PIN31_BITMASK;
        } else if (pin == 32) {
            CORE_PIN32_PORTTOGGLE = CORE_PIN32_BITMASK;
        } else if (pin == 33) {
            CORE_PIN33_PORTTOGGLE = CORE_PIN33_BITMASK;
        } else if (pin == 34) {
            CORE_PIN34_PORTTOGGLE = CORE_PIN34_BITMASK;
        } else if (pin == 35) {
            CORE_PIN35_PORTTOGGLE = CORE_PIN35_BITMASK;
        } else if (pin == 36) {
            CORE_PIN36_PORTTOGGLE = CORE_PIN36_BITMASK;
        } else if (pin == 37) {
            CORE_PIN37_PORTTOGGLE = CORE_PIN37_BITMASK;
        } else if (pin == 38) {
            CORE_PIN38_PORTTOGGLE = CORE_PIN38_BITMASK;
        } else if (pin == 39) {
            CORE_PIN39_PORTTOGGLE = CORE_PIN39_BITMASK;
#if CORE_NUM_DIGITAL > 40
        } else if (pin == 40) {
            CORE_PIN40_PORTTOGGLE = CORE_PIN40_BITMASK;
        } else if (pin == 41) {
            CORE_PIN41_PORTTOGGLE = CORE_PIN41_BITMASK;
        } else if (pin == 42) {
            CORE_PIN42_PORTTOGGLE = CORE_PIN42_BITMASK;
        } else if (pin == 43) {
            CORE_PIN43_PORTTOGGLE = CORE_PIN43_BITMASK;
        } else if (pin == 44) {
            CORE_PIN44_PORTTOGGLE = CORE_PIN44_BITMASK;
        } else if (pin == 45) {
            CORE_PIN45_PORTTOGGLE = CORE_PIN45_BITMASK;
#endif
#if CORE_NUM_DIGITAL > 46
        } else if (pin == 46) {
            CORE_PIN46_PORTTOGGLE = CORE_PIN46_BITMASK;
        } else if (pin == 47) {
            CORE_PIN47_PORTTOGGLE = CORE_PIN47_BITMASK;
        } else if (pin == 48) {
            CORE_PIN48_PORTTOGGLE = CORE_PIN48_BITMASK;
        } else if (pin == 49) {
            CORE_PIN49_PORTTOGGLE = CORE_PIN49_BITMASK;
        } else if (pin == 50) {
            CORE_PIN50_PORTTOGGLE = CORE_PIN50_BITMASK;
        } else if (pin == 51) {
            CORE_PIN51_PORTTOGGLE = CORE_PIN51_BITMASK;
        } else if (pin == 52) {
            CORE_PIN52_PORTTOGGLE = CORE_PIN52_BITMASK;
        } else if (pin == 53) {
            CORE_PIN53_PORTTOGGLE = CORE_PIN53_BITMASK;
        } else if (pin == 54) {
            CORE_PIN54_PORTTOGGLE = CORE_PIN54_BITMASK;
        } else if (pin == 55) {
            CORE_PIN55_PORTTOGGLE = CORE_PIN55_BITMASK;
#endif
        }
    } else {
        digitalToggle(pin);
    }
}

Relevant modified sections of digital.c:

Code:
const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[] = {
    {&CORE_PIN0_PORTREG, &CORE_PIN0_CONFIG, &CORE_PIN0_PADCONFIG, CORE_PIN0_BITMASK},
    {&CORE_PIN1_PORTREG, &CORE_PIN1_CONFIG, &CORE_PIN1_PADCONFIG, CORE_PIN1_BITMASK},
    {&CORE_PIN2_PORTREG, &CORE_PIN2_CONFIG, &CORE_PIN2_PADCONFIG, CORE_PIN2_BITMASK},
    {&CORE_PIN3_PORTREG, &CORE_PIN3_CONFIG, &CORE_PIN3_PADCONFIG, CORE_PIN3_BITMASK},
    {&CORE_PIN4_PORTREG, &CORE_PIN4_CONFIG, &CORE_PIN4_PADCONFIG, CORE_PIN4_BITMASK},
    {&CORE_PIN5_PORTREG, &CORE_PIN5_CONFIG, &CORE_PIN5_PADCONFIG, CORE_PIN5_BITMASK},
    {&CORE_PIN6_PORTREG, &CORE_PIN6_CONFIG, &CORE_PIN6_PADCONFIG, CORE_PIN6_BITMASK},
    {&CORE_PIN7_PORTREG, &CORE_PIN7_CONFIG, &CORE_PIN7_PADCONFIG, CORE_PIN7_BITMASK},
    {&CORE_PIN8_PORTREG, &CORE_PIN8_CONFIG, &CORE_PIN8_PADCONFIG, CORE_PIN8_BITMASK},
    {&CORE_PIN9_PORTREG, &CORE_PIN9_CONFIG, &CORE_PIN9_PADCONFIG, CORE_PIN9_BITMASK},
    {&CORE_PIN10_PORTREG, &CORE_PIN10_CONFIG, &CORE_PIN10_PADCONFIG, CORE_PIN10_BITMASK},
    {&CORE_PIN11_PORTREG, &CORE_PIN11_CONFIG, &CORE_PIN11_PADCONFIG, CORE_PIN11_BITMASK},
    {&CORE_PIN12_PORTREG, &CORE_PIN12_CONFIG, &CORE_PIN12_PADCONFIG, CORE_PIN12_BITMASK},
    {&CORE_PIN13_PORTREG, &CORE_PIN13_CONFIG, &CORE_PIN13_PADCONFIG, CORE_PIN13_BITMASK},
    {&CORE_PIN14_PORTREG, &CORE_PIN14_CONFIG, &CORE_PIN14_PADCONFIG, CORE_PIN14_BITMASK},
    {&CORE_PIN15_PORTREG, &CORE_PIN15_CONFIG, &CORE_PIN15_PADCONFIG, CORE_PIN15_BITMASK},
    {&CORE_PIN16_PORTREG, &CORE_PIN16_CONFIG, &CORE_PIN16_PADCONFIG, CORE_PIN16_BITMASK},
    {&CORE_PIN17_PORTREG, &CORE_PIN17_CONFIG, &CORE_PIN17_PADCONFIG, CORE_PIN17_BITMASK},
    {&CORE_PIN18_PORTREG, &CORE_PIN18_CONFIG, &CORE_PIN18_PADCONFIG, CORE_PIN18_BITMASK},
    {&CORE_PIN19_PORTREG, &CORE_PIN19_CONFIG, &CORE_PIN19_PADCONFIG, CORE_PIN19_BITMASK},
    {&CORE_PIN20_PORTREG, &CORE_PIN20_CONFIG, &CORE_PIN20_PADCONFIG, CORE_PIN20_BITMASK},
    {&CORE_PIN21_PORTREG, &CORE_PIN21_CONFIG, &CORE_PIN21_PADCONFIG, CORE_PIN21_BITMASK},
    {&CORE_PIN22_PORTREG, &CORE_PIN22_CONFIG, &CORE_PIN22_PADCONFIG, CORE_PIN22_BITMASK},
    {&CORE_PIN23_PORTREG, &CORE_PIN23_CONFIG, &CORE_PIN23_PADCONFIG, CORE_PIN23_BITMASK},
    {&CORE_PIN24_PORTREG, &CORE_PIN24_CONFIG, &CORE_PIN24_PADCONFIG, CORE_PIN24_BITMASK},
    {&CORE_PIN25_PORTREG, &CORE_PIN25_CONFIG, &CORE_PIN25_PADCONFIG, CORE_PIN25_BITMASK},
    {&CORE_PIN26_PORTREG, &CORE_PIN26_CONFIG, &CORE_PIN26_PADCONFIG, CORE_PIN26_BITMASK},
    {&CORE_PIN27_PORTREG, &CORE_PIN27_CONFIG, &CORE_PIN27_PADCONFIG, CORE_PIN27_BITMASK},
    {&CORE_PIN28_PORTREG, &CORE_PIN28_CONFIG, &CORE_PIN28_PADCONFIG, CORE_PIN28_BITMASK},
    {&CORE_PIN29_PORTREG, &CORE_PIN29_CONFIG, &CORE_PIN29_PADCONFIG, CORE_PIN29_BITMASK},
    {&CORE_PIN30_PORTREG, &CORE_PIN30_CONFIG, &CORE_PIN30_PADCONFIG, CORE_PIN30_BITMASK},
    {&CORE_PIN31_PORTREG, &CORE_PIN31_CONFIG, &CORE_PIN31_PADCONFIG, CORE_PIN31_BITMASK},
    {&CORE_PIN32_PORTREG, &CORE_PIN32_CONFIG, &CORE_PIN32_PADCONFIG, CORE_PIN32_BITMASK},
    {&CORE_PIN33_PORTREG, &CORE_PIN33_CONFIG, &CORE_PIN33_PADCONFIG, CORE_PIN33_BITMASK},
    {&CORE_PIN34_PORTREG, &CORE_PIN34_CONFIG, &CORE_PIN34_PADCONFIG, CORE_PIN34_BITMASK},
    {&CORE_PIN35_PORTREG, &CORE_PIN35_CONFIG, &CORE_PIN35_PADCONFIG, CORE_PIN35_BITMASK},
    {&CORE_PIN36_PORTREG, &CORE_PIN36_CONFIG, &CORE_PIN36_PADCONFIG, CORE_PIN36_BITMASK},
    {&CORE_PIN37_PORTREG, &CORE_PIN37_CONFIG, &CORE_PIN37_PADCONFIG, CORE_PIN37_BITMASK},
    {&CORE_PIN38_PORTREG, &CORE_PIN38_CONFIG, &CORE_PIN38_PADCONFIG, CORE_PIN38_BITMASK},
    {&CORE_PIN39_PORTREG, &CORE_PIN39_CONFIG, &CORE_PIN39_PADCONFIG, CORE_PIN39_BITMASK},
#if CORE_NUM_DIGITAL > 40
    {&CORE_PIN40_PORTREG, &CORE_PIN40_CONFIG, &CORE_PIN40_PADCONFIG, CORE_PIN40_BITMASK},
    {&CORE_PIN41_PORTREG, &CORE_PIN41_CONFIG, &CORE_PIN41_PADCONFIG, CORE_PIN41_BITMASK},
    {&CORE_PIN42_PORTREG, &CORE_PIN42_CONFIG, &CORE_PIN42_PADCONFIG, CORE_PIN42_BITMASK},
    {&CORE_PIN43_PORTREG, &CORE_PIN43_CONFIG, &CORE_PIN43_PADCONFIG, CORE_PIN43_BITMASK},
    {&CORE_PIN44_PORTREG, &CORE_PIN44_CONFIG, &CORE_PIN44_PADCONFIG, CORE_PIN44_BITMASK},
    {&CORE_PIN45_PORTREG, &CORE_PIN45_CONFIG, &CORE_PIN45_PADCONFIG, CORE_PIN45_BITMASK},
#endif
#if CORE_NUM_DIGITAL > 46
    {&CORE_PIN46_PORTREG, &CORE_PIN46_CONFIG, &CORE_PIN46_PADCONFIG, CORE_PIN46_BITMASK},
    {&CORE_PIN47_PORTREG, &CORE_PIN47_CONFIG, &CORE_PIN47_PADCONFIG, CORE_PIN47_BITMASK},
    {&CORE_PIN48_PORTREG, &CORE_PIN48_CONFIG, &CORE_PIN48_PADCONFIG, CORE_PIN48_BITMASK},
    {&CORE_PIN49_PORTREG, &CORE_PIN49_CONFIG, &CORE_PIN49_PADCONFIG, CORE_PIN49_BITMASK},
    {&CORE_PIN50_PORTREG, &CORE_PIN50_CONFIG, &CORE_PIN50_PADCONFIG, CORE_PIN50_BITMASK},
    {&CORE_PIN51_PORTREG, &CORE_PIN51_CONFIG, &CORE_PIN51_PADCONFIG, CORE_PIN51_BITMASK},
    {&CORE_PIN52_PORTREG, &CORE_PIN52_CONFIG, &CORE_PIN52_PADCONFIG, CORE_PIN52_BITMASK},
    {&CORE_PIN53_PORTREG, &CORE_PIN53_CONFIG, &CORE_PIN53_PADCONFIG, CORE_PIN53_BITMASK},
    {&CORE_PIN54_PORTREG, &CORE_PIN54_CONFIG, &CORE_PIN54_PADCONFIG, CORE_PIN54_BITMASK},
    {&CORE_PIN55_PORTREG, &CORE_PIN55_CONFIG, &CORE_PIN55_PADCONFIG, CORE_PIN55_BITMASK},
#endif
};

Here's a fresh proof-of-weirdness sketch:

Code:
#include <Arduino.h>

const int inputPin = 55;

void dumpXbarPins() {

    Serial.printf("XBAR pins:");
        for (uint8_t i = 0; i < count_pin_to_xbar_info; i++) {
      Serial.printf(" %u", pin_to_xbar_info[i].pin);
    }
    Serial.println("\n");

}

void setup() {

  Serial.begin(0);
  while (!Serial);

  dumpXbarPins();

  Serial.printf("Setting pin %u INPUT.\n\n", inputPin);
  pinMode(inputPin, INPUT);

  Serial.printf("Starting Serial8.\n\n");
  Serial8.begin(2000000);

  if (Serial8.attachCts(43)) {
    Serial.printf("CTS attached to pin 43.\n");
  } else {
    Serial.printf("*** CTS pin 43 NOT ATTACHED.\n");
  }

}

void loop() {
}

In that sketch as shown exactly above, attachCts(43) returns true. Output as follows:

Code:
XBAR pins: 0 1 2 3 4 5 7 8 30 31 32 33 36 37 42 43 44 45 46 47

Setting pin 55 INPUT.

Starting Serial8.

CTS attached to pin 43.

Now, if you comment out the call to dumpXbarPins() inside the setup() function, the results go bad:

Code:
Setting pin 55 INPUT.

Starting Serial8.

*** CTS pin 43 NOT ATTACHED.

Colour me confused! 🫤
 
I should also mention that I get the same results on a factory Teensy 4.1, eliminating the custom PCB. I'm compiling on a Mac with Apple Silicon.
 
I just tried everything using the Arduino IDE instead of PlatformIO / VSCode (which I've been using) and it works the way it should. Investigating...
 
I've tried lots of things - including the obvious clean/fresh installation of PlatformIO and its Teensy toolchain. Also compared the compiler and compiler flags (Arduino IDE vs PlatformIO). They're using identical compiler versions, compiling with the same C++ standard etc.

The only area where I seem to be able to get any change in behaviour is with changing the optimisation level compiler flag. The default in PlatformIO is -O2. Changing to -O1 works, but turning off optimisation all together causes the compiled binary (.hex / .elf) to not boot once loaded to the IMXRT1062.

I'm completely baffled. Going to move on with the strange workaround for now (accessing the count_pin_to_xbar_info[] table early and at a high level in program execution) but if anyone out there has any experience with this kind of weird stuff with the PlatformIO build system for Teensy 4.1, please pass on any advice!

Thanks again @KurtE for the earlier fix and PR.
 
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