Call to arms | Teensy + SDRAM = true

KurtE · Dec 24, 2023

Looks like you are making progress!

PaulStoffregen · Dec 24, 2023

I spent some time reading the NXP SDK code Defragster posted in msg #10, and also the reference manual.

Here's my initial and incomplete (see SEMC_SDRAMCR2, SEMC_SDRAMCR3, IP commands) attempt to convert it all to Teensy. Hopefully this at least helps get things started...

Code:

unsigned int ns_to_clocks(float ns, float freq)
{
    float clocks = ceilf(ns * 1.0e-9f * freq);
    if (clocks < 1.0f) return 1;
    return (unsigned int)clocks;
}


bool sdram_init()
{
    // use PLL3 PFD1 664.62 divided by 4 or 5, for 166 or 133 MHz
    const unsigned int clockdiv = 5;
    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);
    delayMicroseconds(1);
    const float freq = 664.62e6 / (float)clockdiv;
    CCM_CCGR3 |= CCM_CCGR3_SEMC(CCM_CCGR_ON);

    // software reset
    SEMC_BR0 = 0;
    SEMC_BR1 = 0;
    SEMC_BR2 = 0;
    SEMC_BR3 = 0;
    SEMC_BR4 = 0;
    SEMC_BR5 = 0;
    SEMC_BR6 = 0;
    SEMC_BR7 = 0;
    SEMC_BR8 = 0;
    SEMC_MCR = SEMC_MCR_SWRST;
    elapsedMicros timeout = 0;
    while (SEMC_MCR & SEMC_MCR_SWRST) {
        if (timeout > 1500) return false;
    }

    // configure pins
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 0x10;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 0;
     IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 0x10;
    // TODO: configure pad registers for 200 MHz, fast drive, hyst?
    // TODO: IOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT not needed?

    // turn on SEMC hardware, same settings as NXP's SDK
    SEMC_MCR |= SEMC_MCR_MDIS | SEMC_MCR_CTO(0xFF) | SEMC_MCR_BTO(0x1F);
    // TODO: reference manual page 1364 says "Recommend to set BMCR0 with 0x0 for
    // applications that require restrict sequence of transactions", same on BMCR1
    SEMC_BMCR0 = SEMC_BMCR0_WQOS(5) | SEMC_BMCR0_WAGE(8) |
        SEMC_BMCR0_WSH(0x40) | SEMC_BMCR0_WRWS(0x10);
    SEMC_BMCR1 = SEMC_BMCR1_WQOS(5) | SEMC_BMCR1_WAGE(8) |
        SEMC_BMCR1_WPH(0x60) | SEMC_BMCR1_WRWS(0x24) | SEMC_BMCR1_WBR(0x40);
    SEMC_MCR &= ~SEMC_MCR_MDIS;

    // configure SDRAM parameters
    SEMC_BR0 = 0x80000000 | SEMC_BR_MS(13 /*13 = 32 Mbyte*/) | SEMC_BR_VLD;
    SEMC_SDRAMCR0 = SEMC_SDRAMCR0_CL(3) |
        SEMC_SDRAMCR0_COL(3) |  // 3 = 9 bit column
        SEMC_SDRAMCR0_BL(3) |   // 3 = 8 word burst length
        SEMC_SDRAMCR0_PS;       // use 16 bit data
    SEMC_SDRAMCR1 =
        SEMC_SDRAMCR1_ACT2PRE(ns_to_clocks(42, freq)) | // tRAS: ACTIVE to PRECHARGE
        SEMC_SDRAMCR1_CKEOFF(ns_to_clocks(42, freq)) |  // self refresh
        SEMC_SDRAMCR1_WRC(ns_to_clocks(12, freq)) |     // tWR: WRITE recovery
        SEMC_SDRAMCR1_RFRC(ns_to_clocks(67, freq)) |    // tRFC or tXSR: REFRESH recovery
        SEMC_SDRAMCR1_ACT2RW(ns_to_clocks(18, freq)) |  // tRCD: ACTIVE to READ/WRITE
        SEMC_SDRAMCR1_PRE2ACT(ns_to_clocks(18, freq));  // tRP: PRECHARGE to ACTIVE/REFRESH
    SEMC_SDRAMCR2 = 0; // TODO... page 1425
        //#define SEMC_SDRAMCR2_ITO(n)            ((uint32_t)(n & 0xFF)<<24)
        //#define SEMC_SDRAMCR2_ACT2ACT(n)        ((uint32_t)(n & 0xFF)<<16)
        //#define SEMC_SDRAMCR2_REF2REF(n)        ((uint32_t)(n & 0xFF)<<8)
        //#define SEMC_SDRAMCR2_SRRC(n)           ((uint32_t)(n & 0xFF)<<0)
    SEMC_SDRAMCR3 = 0; // TODO...page 1426
        //#define SEMC_SDRAMCR3_UT(n)             ((uint32_t)(n & 0xFF)<<24)
        //#define SEMC_SDRAMCR3_RT(n)             ((uint32_t)(n & 0xFF)<<16)
        //#define SEMC_SDRAMCR3_PRESCALE(n)       ((uint32_t)(n & 0xFF)<<8)
        //#define SEMC_SDRAMCR3_REBL(n)           ((uint32_t)(n & 0x07)<<1)
        //#define SEMC_SDRAMCR3_REN               ((uint32_t)(1<<0))
    SEMC_IPCR1 = 2; // IP commadns, data is 16 bits wide
    SEMC_IPCR2 = 0;

    // TODO: send IP commands to initialize SDRAM chip
    //  precharge all
    //  auto refresh (NXP SDK sends this twice, why?)
    //  mode set

    // enable refresh
    SEMC_SDRAMCR3 |= SEMC_SDRAMCR3_REN;

    // TODO: configure MPU to allow read/write, disallow exec, use cache

    return true; // hopefully SDRAM now working at 80000000 to 81FFFFFF
}


void setup() {
    Serial.begin(9600);
    Serial.println("SDRAM Init Experiment");
    if (sdram_init()) {
        Serial.println(":-)");
    } else {
        Serial.println("nope :(");
    }
}

void loop() {

}

PaulStoffregen · Dec 24, 2023

Oh, forgot to substract 1 after those ns_to_clocks() since the hardware adds 1 clock. But shouldn't really matter, just slightly slower timing.

Anyway, probably done fiddling with this until after Christmas, but wanted to share the incomplete code in case anyone else wants to actually try it and fill in the rest.

EDIT: also grab the latest imxrt.h from github, which fixes a silly typo I made last night.

mjs513 · Dec 24, 2023

PaulStoffregen said:
Here's my initial and incomplete (see SEMC_SDRAMCR2, SEMC_SDRAMCR3, IP commands) attempt to convert it all to Teensy. Hopefully this at least helps get things started...

Thanks Paul
Was beginning to work on it but getting busy for the holiday today. This I what I got from going through the example:

Code:

FLASHMEM void configure_sdram_pins()
{
    // initialize pins
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0x0110F9;   //SEMC_D0
                                                /* Slew Rate Field: Fast Slew Rate
                                                 Drive Strength Field: R0/7
                                                 Speed Field: max(200MHz)
                                                 Open Drain Enable Field: Open Drain Disabled
                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
                                                 Pull / Keep Select Field: Keeper
                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                 Hyst. Enable Field: Hysteresis Enabled */
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 0x0110F9;   //SEMC_D0
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 0x0110F9;   //SEMC_D1
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 0x0110F9;   //SEMC_D2
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 0x0110F9;   //SEMC_D3
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 0x0110F9;   //SEMC_D4
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 0x0110F9;   //SEMC_D5
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 0x0110F9;   //SEMC_D6
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 0x0110F9;   //SEMC_DMO
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 0x0110F9;   //SEMC_A0
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 0x0110F9;   //SEMC_A1
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 0x0110F9;   //SEMC_A2
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 0x0110F9;   //SEMC_A3
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 0x0110F9;   //SEMC_A4
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 0x0110F9;   //SEMC_A5
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 0x0110F9;   //SEMC_A6
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 0x0110F9;   //SEMC_A7
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 0x0110F9;   //SEMC_A8
   
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 0x0110F9;   //SEMC_A9
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 0x0110F9;   //SEMC_A11
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 0x0110F9;   //SEMC_A12
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 0x0110F9;   //SEMC_BA0
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 0x0110F9;   //SEMC_BA1
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 0x0110F9;   //SEMC_A10
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 0x0110F9;   //SEMC_CAS
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 0x0110F9;   //SEMC_RAS
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 0x0110F9;   //SEMC_CLK
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 0x0110F9;   //SEMC_CKE
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 0x0110F9;   //SEMC_WE
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 0x0110F9;   //SEMC_CS0
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 0x0110F9;   //SEMC_D8
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 0x0110F9;   //SEMC_D9
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 0x0110F9;   //SEMC_D10
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 0x0110F9;   //SEMC_D11
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 0x0110F9;   //SEMC_D12
   
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 0x0110F9;   //SEMC_D13
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 0x0110F9;   //SEMC_D14
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 0x0110F9;   //SEMC_D15
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 0x0110F9;   //SEMC_DM1
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 0x0110F9;   //SEMC_DQS
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 0x0110F9;   //SEMC_MD0
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 0x0110F9;   //SEMC_MD1
   
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 0x00;
   
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 0x00;
   
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 0x00;
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 0x00;

}

Looks like there are some differences - will have to investigate more - just started this morning

Mike

EDIT: Think going to have to double check this compared to what they have in the sdk

Code:

  - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, pull_keeper_enable: Enable,
    open_drain: Disable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01, hysteresis_enable: Enable, pull_keeper_enable: Enable, speed: MHZ_200, drive_strength: R0_7,
    slew_rate: Fast}
  - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02, hysteresis_enable: Enable, pull_keeper_enable: Enable, speed: MHZ_200, drive_strength: R0_7,
    slew_rate: Fast}
  - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03, hysteresis_enable: Enable, pull_keeper_enable: Enable, speed: MHZ_200, drive_strength: R0_7,
    slew_rate: Fast}
  - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04, hysteresis_enable: Enable, pull_keeper_enable: Enable, speed: MHZ_200, drive_strength: R0_7,
    slew_rate: Fast}
  - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27, hysteresis_enable: Enable, pull_keeper_select: Keeper, speed: MHZ_200, drive_strength: R0_7,
    slew_rate: Fast}
  - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39, software_input_on: Enable, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7,
    slew_rate: Fast}
  - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}
  - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41, hysteresis_enable: Enable, speed: MHZ_200, drive_strength: R0_7, slew_rate: Fast}

Dogbone06 · Dec 24, 2023

@Paul So it's confirmed that C29 should be removed?

If that's the case, then @defragster, remove this capacitor on the top side. I hope you got a hot air station or an iron.

defragster · Dec 24, 2023

mjs513 said:
I give up - I will play along with the dev. But curiosity got to me and you know what they say "curiosity kills the cat but satisfaction brought him back." But @defragster may have it all done by the time I get the board I'll IM you with my info.

WOW - runaway train! Good to have @PaulStoffregen input/update/assistance and great to have @mjs513 onboard.
Just popping in and there is a page of new posts to catch up on! Including CODE and the cores update.
Going to be tough to ignore it for another day or so ... but Christmas and Wedding Anniversary #35 ...

I was up last night (okay this AM) fiddling with the 16MB PSRAM test to refactor into EVKB 1062 SDRAM testing to see speed diff NOW and have a ready test for all 32MB when that shows signs of life.

mjs513 · Dec 24, 2023

@defragster - @Dogbone06 - @PaulStoffregen
Running out of time for the day but I did a little more work on Paul's sketch - still need to put together the sendIPCmd but... Trying to work off Paul's ToDo list in the sketch.

UPDATED CODE

Code:

#define SDRAM_Read        0x08          /*  SDRAM memory read. */
#define SDRAM_Write       0x09         /*  SDRAM memory write. */
#define SDRAM_Modeset     0x0a       /*  SDRAM MODE SET. */
#define SDRAM_Active      0x0b        /*  SDRAM active. */
#define SDRAM_AutoRefresh 0x0c   /*  SDRAM auto-refresh. */
#define SDRAM_SelfRefresh 0x0d   /*  SDRAM self-refresh. */
#define SDRAM_Precharge   0x0e     /*  SDRAM precharge. */
#define SDRAM_Prechargeall 0x0f  /*  SDRAM precharge all. */
#define SEMC_IPCMD_KEY(n)  (((uint32_t)(((uint32_t)(n)) << 16)) & 0xFFFF0000U)

unsigned int ns_to_clocks(float ns, float freq)
{
    float clocks = ceilf(ns * 1.0e-9f * freq);
    if (clocks < 1.0f) return 1;
    return (unsigned int)clocks;
}
bool SendIPCommand(uint32_t address, uint16_t command, uint32_t write, uint32_t *read)
{
    uint32_t cmdMode;
    bool readCmd = 0;
    bool writeCmd = 0;
    /* Clear status bit */
    SEMC_INTR |= 0x1U;
    /* Set address. */
    SEMC_IPCR0= address;
    /* Check command mode. */
    cmdMode = command & 0xFU;
    readCmd = (cmdMode == SDRAM_Read);
    writeCmd = (cmdMode == SDRAM_Write) || (cmdMode == SDRAM_Modeset);
    if (writeCmd)
    {
        /* Set data. */
        SEMC_IPTXDAT = write;
    }
    /* Set command code. */
    SEMC_IPCMD = command | SEMC_IPCMD_KEY(0xA55A);
    /* Wait for command done. */
    bool result = IPCommandComplete();
    if (result != true)
    {
        return result;
    }
    if (readCmd)
    {
        /* Get the read data */
        *read = SEMC_IPRXDAT;
    }
    return true;
}
bool IPCommandComplete()
{
    /* Poll status bit till command is done*/
    while (!(SEMC_INTR & 0x1))
    {
    };
    /* Clear status bit */
    SEMC_INTR |= 0x1;
    /* Check error status */
    if (SEMC_INTR & 0x2)
    {
        SEMC_INTR |= 0x2;
        return false;
    }
    return true;
}
bool sdram_init()
{
    // use PLL3 PFD1 664.62 divided by 4 or 5, for 166 or 133 MHz
    const unsigned int clockdiv = 5;
    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);
    delayMicroseconds(1);
    const float freq = 664.62e6 / (float)clockdiv;
    CCM_CCGR3 |= CCM_CCGR3_SEMC(CCM_CCGR_ON);
    // software reset
    SEMC_BR0 = 0;
    SEMC_BR1 = 0;
    SEMC_BR2 = 0;
    SEMC_BR3 = 0;
    SEMC_BR4 = 0;
    SEMC_BR5 = 0;
    SEMC_BR6 = 0;
    SEMC_BR7 = 0;
    SEMC_BR8 = 0;
    SEMC_MCR = SEMC_MCR_SWRST;
    elapsedMicros timeout = 0;
    while (SEMC_MCR & SEMC_MCR_SWRST) {
        if (timeout > 1500) return false;
    }
    configure_sdram_pins();
    // TODO: configure pad registers for 200 MHz, fast drive, hyst?
    // TODO: IOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT not needed?
    // turn on SEMC hardware, same settings as NXP's SDK
    SEMC_MCR |= SEMC_MCR_MDIS | SEMC_MCR_CTO(0xFF) | SEMC_MCR_BTO(0x1F);
    // TODO: reference manual page 1364 says "Recommend to set BMCR0 with 0x0 for
    // applications that require restrict sequence of transactions", same on BMCR1
    SEMC_BMCR0 = SEMC_BMCR0_WQOS(5) | SEMC_BMCR0_WAGE(8) |
        SEMC_BMCR0_WSH(0x40) | SEMC_BMCR0_WRWS(0x10);
    SEMC_BMCR1 = SEMC_BMCR1_WQOS(5) | SEMC_BMCR1_WAGE(8) |
        SEMC_BMCR1_WPH(0x60) | SEMC_BMCR1_WRWS(0x24) | SEMC_BMCR1_WBR(0x40);
    SEMC_MCR &= ~SEMC_MCR_MDIS;
    // configure SDRAM parameters
    SEMC_BR0 = 0x80000000 | SEMC_BR_MS(13 /*13 = 32 Mbyte*/) | SEMC_BR_VLD;
    SEMC_SDRAMCR0 = SEMC_SDRAMCR0_CL(3) |
        SEMC_SDRAMCR0_COL(3) |  // 3 = 9 bit column
        SEMC_SDRAMCR0_BL(3) |   // 3 = 8 word burst length
        SEMC_SDRAMCR0_PS;       // use 16 bit data
    SEMC_SDRAMCR1 =
        SEMC_SDRAMCR1_ACT2PRE(ns_to_clocks(42, freq)) | // tRAS: ACTIVE to PRECHARGE
        SEMC_SDRAMCR1_CKEOFF(ns_to_clocks(42, freq)) |  // self refresh
        SEMC_SDRAMCR1_WRC(ns_to_clocks(12, freq)) |     // tWR: WRITE recovery
        SEMC_SDRAMCR1_RFRC(ns_to_clocks(67, freq)) |    // tRFC or tXSR: REFRESH recovery
        SEMC_SDRAMCR1_ACT2RW(ns_to_clocks(18, freq)) |  // tRCD: ACTIVE to READ/WRITE
        SEMC_SDRAMCR1_PRE2ACT(ns_to_clocks(18, freq));  // tRP: PRECHARGE to ACTIVE/REFRESH
    SEMC_SDRAMCR2 = 0; // TODO... page 1425
        //#define SEMC_SDRAMCR2_ITO(n)            ((uint32_t)(n & 0xFF)<<24)
        //#define SEMC_SDRAMCR2_ACT2ACT(n)        ((uint32_t)(n & 0xFF)<<16)
        //#define SEMC_SDRAMCR2_REF2REF(n)        ((uint32_t)(n & 0xFF)<<8)
        //#define SEMC_SDRAMCR2_SRRC(n)           ((uint32_t)(n & 0xFF)<<0)
    SEMC_SDRAMCR3 = 0; // TODO...page 1426
        //#define SEMC_SDRAMCR3_UT(n)             ((uint32_t)(n & 0xFF)<<24)
        //#define SEMC_SDRAMCR3_RT(n)             ((uint32_t)(n & 0xFF)<<16)
        //#define SEMC_SDRAMCR3_PRESCALE(n)       ((uint32_t)(n & 0xFF)<<8)
        //#define SEMC_SDRAMCR3_REBL(n)           ((uint32_t)(n & 0x07)<<1)
        //#define SEMC_SDRAMCR3_REN               ((uint32_t)(1<<0))
   SEMC_SDRAMCR2 =
        SEMC_SDRAMCR2_SRRC((ns_to_clocks(67, freq) - 1)) |
        SEMC_SDRAMCR2_REF2REF(ns_to_clocks(60, freq)) |           /* No Minus one to keep with RM */
        SEMC_SDRAMCR2_ACT2ACT(ns_to_clocks(60, freq)) | /* No Minus one to keep with RM */
        SEMC_SDRAMCR2_ITO(0); 
  //sdk has: idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns
  //RM states
/*   SEMC closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is
considered idle when there is no AXI Bus transfer and no SDRAM command pending.
00000000b - IDLE timeout period is 256*Prescale period.
00000001-11111111b - IDLE timeout period is ITO*Prescale period.
*/
    uint32_t prescaleperiod = 160 * (1000000000 / freq);
    uint16_t prescale = prescaleperiod / 16 / (1000000000 / freq);
    if (prescale > 256)
    {
        Serial.println("Invalid Timer Setting");
        while(1){}
    }
    uint16_t refresh = (64 * 1000000 / 8192)/ prescaleperiod;
    uint16_t urgentRef = refresh;
    //uint16_t idle = 0 / prescaleperiod;
    
    SEMC_SDRAMCR3 = SEMC_SDRAMCR3_REBL((1 - 1)) |
                     /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */
                     SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef);
    SEMC_IPCR1 = 2; // IP commadns, data is 16 bits wide
    SEMC_IPCR2 = 0;
    // TODO: send IP commands to initialize SDRAM chip
    //  precharge all
    //  auto refresh (NXP SDK sends this twice, why?)
    //  mode set
    bool result_cmd = SendIPCommand(0x80000000, SDRAM_Prechargeall, 0, NULL);
    if (result_cmd != true)
    {
        return result_cmd;
    }
    result_cmd = SendIPCommand(0x80000000, SDRAM_AutoRefresh, 0, NULL);
    if (result_cmd != true)
    {
        return result_cmd;
    }
    result_cmd = SendIPCommand(0x80000000, SDRAM_AutoRefresh, 0, NULL);
    if (result_cmd != true)
    {
        return result_cmd;
    }
    /* Mode setting value. */
    uint16_t mode = (uint16_t)3| (uint16_t)(3 << 4);
    result_cmd = SendIPCommand(0x80000000, SDRAM_Modeset, mode, NULL);
    if (result_cmd != true)
    {
        return result_cmd;
    }
    // enable refresh
    SEMC_SDRAMCR3 |= SEMC_SDRAMCR3_REN;
    // TODO: configure MPU to allow read/write, disallow exec, use cache
    if(result_cmd == false) return false;
    return true; // hopefully SDRAM now working at 80000000 to 81FFFFFF
}

void setup() {
    Serial.begin(9600);
    Serial.println("SDRAM Init Experiment");
    if (sdram_init()) {
        Serial.println(":-)");
    } else {
        Serial.println("nope :(");
    }
}
void loop() {
}
void configure_sdram_pins()
{
  // initialize pins
    IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0x0110F9;   //SEMC_D0
                                                /* Slew Rate Field: Fast Slew Rate
                                                 Drive Strength Field: R0/7
                                                 Speed Field: max(200MHz)
                                                 Open Drain Enable Field: Open Drain Disabled
                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
                                                 Pull / Keep Select Field: Keeper
                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                 Hyst. Enable Field: Hysteresis Enabled */
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 0x0110F9;   //SEMC_D0
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 0x0110F9;   //SEMC_D1
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 0x0110F9;   //SEMC_D2
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 0x0110F9;   //SEMC_D3
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 0x0110F9;   //SEMC_D4
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 0x0110F9;   //SEMC_D5
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 0x0110F9;   //SEMC_D6
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 0x0110F9;   //SEMC_DMO
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 0x0110F9;   //SEMC_A0
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 0x0110F9;   //SEMC_A1
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 0x0110F9;   //SEMC_A2
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 0x0110F9;   //SEMC_A3
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 0x0110F9;   //SEMC_A4
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 0x0110F9;   //SEMC_A5
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 0x0110F9;   //SEMC_A6
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 0x0110F9;   //SEMC_A7
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 0x0110F9;   //SEMC_A8
    
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 0x0110F9;   //SEMC_A9
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 0x0110F9;   //SEMC_A11
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 0x0110F9;   //SEMC_A12
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 0x0110F9;   //SEMC_BA0
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 0x0110F9;   //SEMC_BA1
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 0x0110F9;   //SEMC_A10
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 0x0110F9;   //SEMC_CAS
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 0x0110F9;   //SEMC_RAS
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 0x0110F9;   //SEMC_CLK
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 0x0110F9;   //SEMC_CKE
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 0x0110F9;   //SEMC_WE
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 0x0110F9;   //SEMC_CS0
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 0x0110F9;   //SEMC_D8
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 0x0110F9;   //SEMC_D9
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 0x0110F9;   //SEMC_D10
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 0x0110F9;   //SEMC_D11
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 0x0110F9;   //SEMC_D12
    
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 0x0110F9;   //SEMC_D13
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 0x0110F9;   //SEMC_D14
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 0x0110F9;   //SEMC_D15
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 0x0110F9;   //SEMC_DM1
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 0x0110F9;   //SEMC_DQS
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 0x0110F9;   //SEMC_MD0
  IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 0x0110F9;   //SEMC_MD1
/* Default to Pauls version
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 0x00;
    
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 0x00;
    
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 0x00;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 0x00;
*/
// configure pins
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 0x10;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 0;
  IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 0x10;
}

mjs513 · Dec 24, 2023

Ok I updated the code in my previous post so now it is setup with sendipcommands. The only thing left is:

// TODO: configure MPU to allow read/write, disallow exec, use cache

PaulStoffregen · Dec 24, 2023

For MPU, probably easiest to add this to configure_cache() in startup.c

Code:

        SCB_MPU_RBAR = 0x80000000 | REGION(i++); // SDRAM
        SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_32M;

defragster · Dec 24, 2023

I made {with MIT license for PJRC's sake}: DevBd V4 for SDRAM github: Defragster/EVKB_1060
Now public. DOCS shows the pins as placed on PCB and as referred to T_MM design the bootloader sets given 16MB Flash.
src has the updated imxrt.h and code above p# 57

Pins noted based on PinTest code triggering known pins and then @luni T_MM PinList in a txt file noting those found and missing, assume moved to SDRAM pads - not yet confirmed.

Dogbone06 said:
@Paul So it's confirmed that C29 should be removed?

If that's the case, then @defragster, remove this capacitor on the top side. I hope you got a hot air station or an iron.

I see that little cap - I have an iron ... if I get it off it'll never go back on ... will wait a day or so for confirmation.
I just added standoffs for the bottom to make sure my desk can't break or short anything.

defragster · Dec 24, 2023

Added p#59 MPU note to the .c file on github

Finally spent a minute putting the Teensy PSRAM test into NXP IDE - big issue with the micros() hacked using CYCCNT/600!
Added @manitou code to use int clock ticks - IDE MADE THAT HARD ... IDE UI to add "fsl_gpt" driver total fail ... so just dropped the .c and .h into the project 'drivers' folder and then the build could find it!

So same 'sketch' with ifdef's Teensy PSRAM and EVKB SDRAM. Tried malloc() for smaller DMA and it keeps faulting?

But seems like success: see src/teensyEVKB_xRAM_memtest.ino
> "#define TeensySketch 1" uncommented at top easy peezy in Arduino IDE
> MCUex Project for 10+MB zip to get a build: SEMC_SDK_PROJ24Dec.zip here

T_4.1 PSRAM 16MB- with two summary samples:

test Pattern 00000000 Write 650314 us Read/Test 589825 us
test RndSeed 2976674124 Write 654314 us Read/Test 617310 us
test ran for 72.08 seconds
All memory tests passed

EVKB SDRAM 16MB - with two summary samples:

test Pattern 00000000 Write 51837 us Read/Test 150381 us
test RndSeed 2976674124 Write 146802 us Read/Test 254228 us
test ran for 20.27 seconds
All memory tests passed
SEMC SDRAM Example End.

Calc of the Psudo Rand values is WAY slower on EVKB - it is full debug build and not sure I got 'Optimize 0' removed.
So for FIXED pattern:
> that is 16 MB writes in 51ms versus 650 ms >> 313 MB/sec .vs. 24.6 MB/sec
> that is 16 MB read/test in 150ms versus 589 ms >> 106 MB/sec .vs. 27 MB/sec

And full run edited PSRAM tracking write and then read/test time loops:

test Pattern 5A698421 Write 651565 us Read/Test 589824 us
test Pattern 55555555 Write 650310 us Read/Test 589825 us
test Pattern 33333333 Write 650326 us Read/Test 589825 us
test Pattern 0F0F0F0F Write 650323 us Read/Test 589825 us
test Pattern 00FF00FF Write 650327 us Read/Test 589825 us
test Pattern 0000FFFF Write 650330 us Read/Test 589825 us
test Pattern AAAAAAAA Write 650331 us Read/Test 589825 us
test Pattern CCCCCCCC Write 650324 us Read/Test 589825 us
test Pattern F0F0F0F0 Write 650323 us Read/Test 589825 us
test Pattern FF00FF00 Write 650327 us Read/Test 589825 us
test Pattern FFFF0000 Write 650310 us Read/Test 589825 us
test Pattern FFFFFFFF Write 650328 us Read/Test 589825 us
test Pattern 00000000 Write 650314 us Read/Test 589825 us
test RndSeed 2976674124 Write 654314 us Read/Test 617310 us
test RndSeed 1438200953 Write 654320 us Read/Test 617309 us
test RndSeed 3413783263 Write 656345 us Read/Test 617310 us
test RndSeed 1900517911 Write 654325 us Read/Test 617310 us
test RndSeed 1227909400 Write 654335 us Read/Test 617309 us
test RndSeed 276562754 Write 654321 us Read/Test 617309 us
test RndSeed 146878114 Write 654316 us Read/Test 617310 us
test RndSeed 615545407 Write 654314 us Read/Test 617309 us
test RndSeed 110497896 Write 654309 us Read/Test 617309 us
test RndSeed 74539250 Write 654315 us Read/Test 617309 us
test RndSeed 4197336575 Write 654321 us Read/Test 617310 us
test RndSeed 2280382233 Write 654304 us Read/Test 617309 us
test RndSeed 542894183 Write 654320 us Read/Test 617310 us
test RndSeed 3978544245 Write 654323 us Read/Test 617310 us
test RndSeed 2315909796 Write 654325 us Read/Test 617310 us
test RndSeed 3736286001 Write 654308 us Read/Test 617310 us
test RndSeed 2876690683 Write 654329 us Read/Test 617309 us
test RndSeed 215559886 Write 654319 us Read/Test 617310 us
test RndSeed 539179291 Write 654305 us Read/Test 617309 us
test RndSeed 537678650 Write 654313 us Read/Test 617310 us
test RndSeed 4001405270 Write 654308 us Read/Test 617310 us
test RndSeed 2169216599 Write 655318 us Read/Test 617310 us
test RndSeed 4036891097 Write 654318 us Read/Test 617310 us
test RndSeed 1535452389 Write 654310 us Read/Test 617309 us
test RndSeed 2959727213 Write 654306 us Read/Test 617309 us
test RndSeed 4219363395 Write 654332 us Read/Test 617309 us
test RndSeed 1036929753 Write 654314 us Read/Test 617309 us
test RndSeed 2125248865 Write 654306 us Read/Test 617310 us
test RndSeed 3177905864 Write 654319 us Read/Test 617309 us
test RndSeed 2399307098 Write 654315 us Read/Test 617309 us
test RndSeed 3847634607 Write 654315 us Read/Test 617310 us
test RndSeed 27467969 Write 654324 us Read/Test 617310 us
test RndSeed 520563506 Write 654324 us Read/Test 617310 us
test RndSeed 381313790 Write 654315 us Read/Test 617310 us
test RndSeed 4174769276 Write 656346 us Read/Test 617309 us
test RndSeed 3932189449 Write 654319 us Read/Test 617310 us
test RndSeed 4079717394 Write 654313 us Read/Test 617310 us
test RndSeed 868357076 Write 654309 us Read/Test 617310 us
test RndSeed 2474062993 Write 654312 us Read/Test 617309 us
test RndSeed 1502682190 Write 654316 us Read/Test 617310 us
test RndSeed 2471230478 Write 656343 us Read/Test 617310 us
test RndSeed 85016565 Write 654330 us Read/Test 617310 us
test RndSeed 1427530695 Write 654318 us Read/Test 617309 us
test RndSeed 1100533073 Write 654325 us Read/Test 617309 us
test ran for 72.08 seconds
All memory tests passed

And EVKB SDRAM:

test Pattern 5A698421 Write 51842 us Read/Test 150170 us
test Pattern 55555555 Write 51840 us Read/Test 150381 us
test Pattern 33333333 Write 51831 us Read/Test 150382 us
test Pattern 0F0F0F0F Write 51837 us Read/Test 150383 us
test Pattern 00FF00FF Write 51834 us Read/Test 150382 us
test Pattern 0000FFFF Write 51839 us Read/Test 150381 us
test Pattern AAAAAAAA Write 51838 us Read/Test 150383 us
test Pattern CCCCCCCC Write 51835 us Read/Test 150382 us
test Pattern F0F0F0F0 Write 51837 us Read/Test 150383 us
test Pattern FF00FF00 Write 51836 us Read/Test 150381 us
test Pattern FFFF0000 Write 51837 us Read/Test 150383 us
test Pattern FFFFFFFF Write 51834 us Read/Test 150381 us
test Pattern 00000000 Write 51837 us Read/Test 150381 us
test RndSeed 2976674124 Write 146802 us Read/Test 254228 us
test RndSeed 1438200953 Write 146801 us Read/Test 254208 us
test RndSeed 3413783263 Write 146801 us Read/Test 254228 us
test RndSeed 1900517911 Write 146800 us Read/Test 254226 us
test RndSeed 1227909400 Write 146801 us Read/Test 254216 us
test RndSeed 276562754 Write 146800 us Read/Test 254206 us
test RndSeed 146878114 Write 146801 us Read/Test 254199 us
test RndSeed 615545407 Write 146801 us Read/Test 254194 us
test RndSeed 110497896 Write 146801 us Read/Test 254191 us
test RndSeed 74539250 Write 146801 us Read/Test 254200 us
test RndSeed 4197336575 Write 146801 us Read/Test 254196 us
test RndSeed 2280382233 Write 146801 us Read/Test 254232 us
test RndSeed 542894183 Write 146800 us Read/Test 254196 us
test RndSeed 3978544245 Write 146800 us Read/Test 254187 us
test RndSeed 2315909796 Write 146801 us Read/Test 254200 us
test RndSeed 3736286001 Write 146801 us Read/Test 254204 us
test RndSeed 2876690683 Write 146801 us Read/Test 254231 us
test RndSeed 215559886 Write 146800 us Read/Test 254215 us
test RndSeed 539179291 Write 146801 us Read/Test 254209 us
test RndSeed 537678650 Write 146801 us Read/Test 254222 us
test RndSeed 4001405270 Write 146801 us Read/Test 254232 us
test RndSeed 2169216599 Write 146801 us Read/Test 254213 us
test RndSeed 4036891097 Write 146801 us Read/Test 254169 us
test RndSeed 1535452389 Write 146801 us Read/Test 254212 us
test RndSeed 2959727213 Write 146800 us Read/Test 254198 us
test RndSeed 4219363395 Write 146800 us Read/Test 254197 us
test RndSeed 1036929753 Write 146800 us Read/Test 254193 us
test RndSeed 2125248865 Write 146801 us Read/Test 254226 us
test RndSeed 3177905864 Write 146801 us Read/Test 254231 us
test RndSeed 2399307098 Write 146801 us Read/Test 254227 us
test RndSeed 3847634607 Write 146801 us Read/Test 254208 us
test RndSeed 27467969 Write 146801 us Read/Test 254197 us
test RndSeed 520563506 Write 146801 us Read/Test 254203 us
test RndSeed 381313790 Write 146801 us Read/Test 254215 us
test RndSeed 4174769276 Write 146801 us Read/Test 254214 us
test RndSeed 3932189449 Write 146800 us Read/Test 254187 us
test RndSeed 4079717394 Write 146801 us Read/Test 254204 us
test RndSeed 868357076 Write 146801 us Read/Test 254218 us
test RndSeed 2474062993 Write 146801 us Read/Test 254185 us
test RndSeed 1502682190 Write 146800 us Read/Test 254191 us
test RndSeed 2471230478 Write 146801 us Read/Test 254232 us
test RndSeed 85016565 Write 146800 us Read/Test 254232 us
test RndSeed 1427530695 Write 146801 us Read/Test 254208 us
test RndSeed 1100533073 Write 146800 us Read/Test 254202 us
test ran for 20.27 seconds
All memory tests passed
SEMC SDRAM Example End.

PaulStoffregen · Dec 24, 2023

defragster said:
I see that little cap - I have an iron ... if I get it off it'll never go back on ... will wait a day or so for confirmation.

If using the code from msg #52 or msg #57, that pin isn't used and the capacitor does not matter.

To use that pin, change this line:

Code:

    // turn on SEMC hardware, same settings as NXP's SDK
    SEMC_MCR |= SEMC_MCR_MDIS | SEMC_MCR_CTO(0xFF) | SEMC_MCR_BTO(0x1F);

to also set the SEMC_MCR_DQSMD bit, like this:

Code:

    // turn on SEMC hardware, same settings as NXP's SDK
    SEMC_MCR |= SEMC_MCR_MDIS | SEMC_MCR_CTO(0xFF) | SEMC_MCR_BTO(0x1F) | SEMC_MCR_DQSMD;

With the SEMC_MCR_DQSMD bit set, the EMC_39 pin will be used. Then the capacitor matters.

It's difficult to say what the best design should be, but 100nF is definitely far too much. It needs to be removed. Simply leaving that part unpopulated so the EMC_39 pin is left floating should be fine, since that's how NXP built their eval board and it's what NXP people are recommending on their forum, as in msg #49.

If a capacitor is used, it should probably be in the 3pF to 15pF range. Probably the only way to learn what capacitor is best would involve experimental testing. My best guess is whoever designed the NXP eval board probably put that capacitor on the PCB with the intention of doing that sort of testing (or maybe NXP's customers doing that testing, even though NXP's people on their forum are saying to not connect any capacitor at all and aren't suggesting any sort of testing or tuning this capacitance).

The capacitor is expected to matter only for reading. So perhaps a test program might look similar to the PSRAM memory test, but for each pattern it would probably write the entire memory once and then read it all back thousands of times, since we're expecting the problem to manifest as occasional bad reads. It would probably count the total number of incorrect words read to report at the end of all patterns, continuing the test for all patters rather than stopping when any fails. You'd want a total count of errors rather than simple pass/fail, so you could compare results and say one "failed" test gave fewer errors than another.

Testing would probably be done first at 166 MHz with maybe several candidate capacitors spaning at least that 3pF - 15pF range (which admittedly is just from my imagination and not any sort of specs or hard info from NXP... feel free to use your own imagination for the range of capacitors to be tested). Then repeat with overclocking. For example, if using the 396 MHz PLL2 PFD2 source, divide by 2 would give 198 MHz clock. Then if that works, dividing the 664 MHz souce by 3 gives 221 MHz. Just using those 3 clocks and perhaps 5 candidate capactors adds up to running a lengthy memory test many times.

When this stuff is all working, would be really intesting to see results of that sort of testing... if anyone has the patience to actually do it.

But for now, desolder that 100nF capacitor.

Dogbone06 · Dec 24, 2023

@Paul Do you want a board? I’ll send you one for free.

PaulStoffregen · Dec 25, 2023

Right now, no, do not send me anything. Later (like February-March 2024) ask again, if anything more needs to be done.

defragster · Dec 25, 2023

Per p#62 - the cap will come off.
Saw a spec 'as if expected' reads are some multiple slower than reads - that was in my web search to get to 'SEMC' example and I didn't save it or look again. And above test shows that in 313MB/s .vs. 106 MB/s - where some of that is the if 'test' in Read not done on write.
Taking those 'IF (fail) ABORT' lines out of the PSRAM test array was on the list - but that wasn't first priority. Though there is an ARRAY element value for FAILED test to ACCEPT and LOG and LIST those after the above shown 'FIXED' and 'PsuedoRand'. And the code could easily take an edit to repeat read 'x' times before test pass exit.

I have on hand a set of files to github NOW POSTED - boards.txt and imxrt1062_diy.ld {just the T_4.1 so far}
> also a search of 21 files with 25 instances of: ifdef ARDUINO_TEENSY_MICROMOD
> and other obvious files in need of change

Name is WIP sample - perhaps it should not have said Teensy ... but for now it is Christmas.

teensyDIY.name=Teensy DIY SDRAM
#teensyDIY.upload.maximum_size=16515072
teensyDIY.build.board=TEENSY_SDRAM

mjs513 · Dec 25, 2023

Good Morning all and Merry Christmas

See I missed a lot while I slept. Thanks for the detailed set of info Paul. You should have been a Professor.

@defragster - If you make the changes to startup.c (post #59) and run the code in either msg #52 or msg #57 should still run if you use TMM, I think. Would be interesting to see if it works.

EDIT: This was pretty much the approach we used when implementing PSRAM/FLASH on qspi. Trying to mod the whole core for the new board + add sdram may take more debugging effort before you even know if SDRAM is working on the new board. Once that is working then we can mod the board.

mjs513 · Dec 25, 2023

Ok did a dump of the registers and setup from the EVKB for future reference:

Code:

 SEMC SDRAM Example Start!
SEMC_INIT................
(INIT)    busTimeoutCycles: 31, 0x1
 (INIT)    SEMC_MCR_BTO:  0x1f000000, 0x0
(INIT)    dqsMode:  1, SEMC_MCR_DQSMD: 0x4
(INIT) MCR: 0x1f000006
(INIT) BMCR0:  0x104085, BMCR1:  0x40602485
(INIT) Enable SEMC: MCR 0x1f000004

ConfigureSDRAM................

(ConfigureSDRAM)      refreshPeriod_nsPerRow: 7812
(ConfigureSDRAM)      tPrescalePeriod_Ns: 960
(ConfigureSDRAM)      refreshUrgThreshold: 7812
(ConfigureSDRAM)      tIdleTimeout_Ns: 0
(ConfigureSDRAM) refresh: 8
(ConfigureSDRAM) urgentRef: 8
(ConfigureSDRAM) idle: 0

(ConfigureSDRAM)      csxPinMux: 3
(ConfigureSDRAM) iocReg: 0x0
(ConfigureSDRAM)      memsize_kbytes: 32768
(ConfigureSDRAM)     memsize: 13
(ConfigureSDRAM) base->BR[cs]: 0x8000001b
(ConfigureSDRAM)
    burstLen: 3
(ConfigureSDRAM)     casLatency: 3
(ConfigureSDRAM)     columnAddrBitNum: 3
(ConfigureSDRAM)     portSize: 1
(ConfigureSDRAM)     SEMC_SDRAMCR0_BL: 48
(ConfigureSDRAM)     SEMC_SDRAMCR0_COL: 768
(ConfigureSDRAM)     SEMC_SDRAMCR0_CL: 3072
(ConfigureSDRAM) SDRAMCR0: 0xf31

(ConfigureSDRAM) IOCR: 0x0

(ConfigureSDRAM)     Precharge2Act_Ns: 18
(ConfigureSDRAM)     Act2ReadWrite_Ns: 18
(ConfigureSDRAM)     RefreshRecovery_Ns: 67
(ConfigureSDRAM)     WriteRecovery_Ns: 12
(ConfigureSDRAM)     CkeOff_Ns: 42
(ConfigureSDRAM)     Act2Prechage_Ns: 42

(ConfigureSDRAM)     SEMC_SDRAMCR1_PRE2ACT: 2
(ConfigureSDRAM)     SEMC_SDRAMCR1_ACT2RW: 32
(ConfigureSDRAM)     SEMC_SDRAMCR1_RFRC: 2560
(ConfigureSDRAM)     SEMC_SDRAMCR1_RFRC: 2560
(ConfigureSDRAM)     SEMC_SDRAMCR1_WRC: 8192
(ConfigureSDRAM)     SEMC_SDRAMCR1_CKEOFF: 393216
(ConfigureSDRAM)     SEMC_SDRAMCR1_ACT2PRE: 6291456
(ConfigureSDRAM) SDRAMCR1: 0x662a22

(ConfigureSDRAM)     SelfRefRecovery_Ns: 67
(ConfigureSDRAM)     Refresh2Refresh_Ns: 60
(ConfigureSDRAM)     Act2Act_Ns: 60
(ConfigureSDRAM)     idle: 0
(ConfigureSDRAM) SDRAMCR2: 0xa0a0a

(ConfigureSDRAM)      refreshBurstLen: 1
(ConfigureSDRAM)      SEMC_SDRAMCR3_REBL: 0x0
(ConfigureSDRAM)      SEMC_SDRAMCR3_PRESCALE: 0xa00
(ConfigureSDRAM)      SEMC_SDRAMCR3_RT(refresh): 0x80000
(ConfigureSDRAM)      SEMC_SDRAMCR3_UT(refresh): 0x8000000
(ConfigureSDRAM) SDRAMCR3: 0x8080a00

(ConfigureSDRAM) IPCR1: 0x2

(ConfigureSDRAM) IPCR2: 0x0

(ConfigureSDRAM) mode: 51

(ConfigureSDRAM) Enables refresh SDRAMCR3: 0x8080a01

 SEMC SDRAM Memory 32 bit Write Start, Start Address 0x80000000, Data Length 4096 !
    SEMC SDRAM Memory 32 bit Write Time (uS) 130

 SEMC SDRAM Read 32 bit Data Start, Start Address 0x80000000, Data Length 4096 !
    SEMC SDRAM Memory 32 bit Read Time (uS) 231

 SEMC SDRAM 32 bit Data Write and Read Compare Start!
    SEMC SDRAM Memory 32 bit R/W Time (uS) 106
 SEMC SDRAM 32 bit Data Write and Read Compare Succeed!

 SEMC SDRAM Memory 16 bit Write Start, Start Address 0x80000000, Data Length 4096 !
    SEMC SDRAM Memory 16 bit Write Time (uS) 204

 SEMC SDRAM Read 16 bit Data Start, Start Address 0x80000000, Data Length 4096 !

 SEMC SDRAM Memory 16 bit Read Time (uS) 128
 SEMC SDRAM 16 bit Data Write and Read Compare Start!
     SEMC SDRAM Memory 16 bit Read/Write Time (uS) 104
 SEMC SDRAM 16 bit Data Write and Read Compare Succeed!

 SEMC SDRAM Memory 8 bit Write Start, Start Address 0x80000000, Data Length 4096 !
    SEMC SDRAM Memory 8 bit Write Time (uS) 147

 SEMC SDRAM Read 8 bit Data Start, Start Address 0x80000000, Data Length 4096 !
    SEMC SDRAM Memory 8 bit Read Time (uS) 121

 SEMC SDRAM 8 bit Data Write and Read Compare Start!

 SEMC SDRAM 8 bit Data Write and Read Compare Succeed!
    SEMC SDRAM Memory 8 bit Read/Write Time (uS) 5039

 SEMC SDRAM Example End.

defragster · Dec 25, 2023

mjs513 said:
Good Morning all and Merry Christmas

+=1

mjs513 said:
Ok did a dump of the registers and setup from the EVKB for future reference:

Can code for that be posted ?? : https://github.com/Defragster/EVKB_1060/tree/main/src
And is there an equivalent for Board: TEENSY_SDRAM

mjs513 said:
@defragster - If you make the changes to startup.c (post #59) and run the code in either msg #52 or msg #57 should still run if you use TMM, I think. Would be interesting to see if it works.

Sounds very interesting!
Prior version was there in \src - just put copy of src/SDRAM_p57 > also in sketch folder in \examples

About out of time?
is this essential for cache?

SCB_MPU_RBAR = 0x80000000 | REGION(i++); // SDRAM
SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_32M;

needs fixed ... Paren was not MISSING ... it is EXTRA at end of line

SDRAM_p57: In function 'bool sdram_init()':
T:\T_Drive\arduino-1.8.19\hardware\teensy\avr\cores\teensy4/imxrt.h:8540:66: error: expected ';' before ')' token
8540 | #define SEMC_SDRAMCR0_BL ((uint32_t)(n & 0x07)<<4))
| ^
C:\Users\TimLabs\Documents\GitHub\EVKB_1060\examples\SDRAM_p57\SDRAM_p57.ino:109:9: note: in expansion of macro 'SEMC_SDRAMCR0_BL'
109 | SEMC_SDRAMCR0_BL(3) | // 3 = 8 word burst length
| ^~~~~~~~~~~~~~~~
Error compiling for board Teensy 4.1.

defragster · Dec 25, 2023

GOOD RESULT:

SDRAM Init Experiment

from:


void setup() {
    Serial.begin(9600);
    Serial.println("SDRAM Init Experiment");
    if (sdram_init()) {
        Serial.println(":-)");
    } else {
        Serial.println("nope :(");
    }
}

mjs513 · Dec 25, 2023

defragster said:
Can code for that be posted ?? : https://github.com/Defragster/EVKB_1060/tree/main/src
And is there an equivalent for Board: TEENSY_SDRAM

Uploaded the version of fsl_semc.c that I have all the printf in for debugging. No not for TEENSY_SDRAM - may do later

defragster said:
is this essential for cache?

As far as I know,

defragster said:
Paren was not MISSING ... it is EXTRA at end of line

Yep forgot to mention that with everything else going on.

GOOD RESULT:

SDRAM Init Experiment

Click to expand...

Success!!!!!!!! Great sign.

The sketch version does not use the DQS pin as Paul mentioned - if you remove the cap you will have to change a couple of lines around line 111:

Code:

    // turn on SEMC hardware, same settings as NXP's SDK
    SEMC_MCR |= SEMC_MCR_MDIS | SEMC_MCR_CTO(0xFF) | SEMC_MCR_BTO(0x1F);
    // uncomment to enable SEMC_MCR_DQSMD (EMC_39) but make sure you comment out the above line first
    //SEMC_MCR |= SEMC_MCR_MDIS | SEMC_MCR_CTO(0xFF) | SEMC_MCR_BTO(0x1F) | SEMC_MCR_DQSMD;

Going to play around with the sketch a bit more probably make a version 1 of the sketch. Should have volunteered sooner

By the Way.... Happy Anniversary!!!!

mjs513 · Dec 25, 2023

@defragster - @Dogbone06

Created a version 1 of the Teensy_sdram sketch that cleans code up a little and added the test cases that are in the EVKB example.

Be interesting to see if it works

I did check to see if it compiles without errors.

Merry Christmas

Dogbone06 · Dec 25, 2023

mjs513 said:
@defragster - @Dogbone06

Created a version 1 of the Teensy_sdram sketch that cleans code up a little and added the test cases that are in the EVKB example.

Be interesting to see if it works I did check to see if it compiles without errors.

Merry Christmas

Defragster is really the only one that can try. I could try as I have a board but I’m not really up to speed on what files to swap out in the core and such. So I’ll just hang back and let Defragster test until you also get your board.

defragster · Dec 25, 2023

@mjs513: No Problem on sooner - it is all in flux and came quickly - head start here was just enough to grease the wheels and things going quickly!

Great that the SDRAM Experiment shows

NO IDEA WHAT

the Christmas Miracle or a great delusion? Added the p#57 code init to PSRAM/SDRAM(EVKB) sketch:
> built with restore unedited imxrt1062_mm.ld : no association for the SDRAM region ... just sdramconfig.address = 0x80000000;

SDRAM Init Experiment

Compile Time:: T:\T_Drive\tCode\RAM\teensyEVKB_xRAM_memtest\teensyEVKB_xRAM_memtest.ino Dec 25 2023 13:02:47
EXTMEM Memory Test, 16 Mbyte
EXTMEM Memory begin, 80000000
EXTMEM Memory end, 81000000
...
test Pattern 00000000 Write 64278 us Read/Test 176638 us
test RndSeed 2976674124 Write 119371 us Read/Test 278054 us
...
test ran for 20.60 seconds
All memory tests passed

My machine in FLUX - Current https://github.com/Defragster/EVKB_1060/tree/main/examples/teensyEVKB_xRAM_memtest
github updated with that and other misc boards.txt (total fail on 21 files with no _MICROMOD as it has ARDUINO_TEENSY_SDRAM)
> how do we handle 25 edits in 21 files (and added?) for a non-pjrc installed DIY board ???
Here is the FULL SDRAM code output for fun - enjoy reading - time to log off ...

SDRAM Init Experiment
:-)
Compile Time:: T:\T_Drive\tCode\RAM\teensyEVKB_xRAM_memtest\teensyEVKB_xRAM_memtest.ino Dec 25 2023 13:02:47
EXTMEM Memory Test, 16 Mbyte
EXTMEM Memory begin, 80000000 
EXTMEM Memory end, 81000000 
testing with fixed pattern 5A698421
testing with pseudo-random sequence, seed=2976674124
testing with pseudo-random sequence, seed=1438200953
testing with pseudo-random sequence, seed=3413783263
testing with pseudo-random sequence, seed=1900517911
testing with pseudo-random sequence, seed=1227909400
testing with pseudo-random sequence, seed=276562754
testing with pseudo-random sequence, seed=146878114
testing with pseudo-random sequence, seed=615545407
testing with pseudo-random sequence, seed=110497896
testing with pseudo-random sequence, seed=74539250
testing with pseudo-random sequence, seed=4197336575
testing with pseudo-random sequence, seed=2280382233
testing with pseudo-random sequence, seed=542894183
testing with pseudo-random sequence, seed=3978544245
testing with pseudo-random sequence, seed=2315909796
testing with pseudo-random sequence, seed=3736286001
testing with pseudo-random sequence, seed=2876690683
testing with pseudo-random sequence, seed=215559886
testing with pseudo-random sequence, seed=539179291
testing with pseudo-random sequence, seed=537678650
testing with pseudo-random sequence, seed=4001405270
testing with pseudo-random sequence, seed=2169216599
testing with pseudo-random sequence, seed=4036891097
testing with pseudo-random sequence, seed=1535452389
testing with pseudo-random sequence, seed=2959727213
testing with pseudo-random sequence, seed=4219363395
testing with pseudo-random sequence, seed=1036929753
testing with pseudo-random sequence, seed=2125248865
testing with pseudo-random sequence, seed=3177905864
testing with pseudo-random sequence, seed=2399307098
testing with pseudo-random sequence, seed=3847634607
testing with pseudo-random sequence, seed=27467969
testing with pseudo-random sequence, seed=520563506
testing with pseudo-random sequence, seed=381313790
testing with pseudo-random sequence, seed=4174769276
testing with pseudo-random sequence, seed=3932189449
testing with pseudo-random sequence, seed=4079717394
testing with pseudo-random sequence, seed=868357076
testing with pseudo-random sequence, seed=2474062993
testing with pseudo-random sequence, seed=1502682190
testing with pseudo-random sequence, seed=2471230478
testing with pseudo-random sequence, seed=85016565
testing with pseudo-random sequence, seed=1427530695
testing with pseudo-random sequence, seed=1100533073
testing with fixed pattern 55555555
testing with fixed pattern 33333333
testing with fixed pattern 0F0F0F0F
testing with fixed pattern 00FF00FF
testing with fixed pattern 0000FFFF
testing with fixed pattern AAAAAAAA
testing with fixed pattern CCCCCCCC
testing with fixed pattern F0F0F0F0
testing with fixed pattern FF00FF00
testing with fixed pattern FFFF0000
testing with fixed pattern FFFFFFFF
testing with fixed pattern 00000000
test Pattern 5A698421 Write 64380 us Read/Test 176636 us 
test Pattern 55555555 Write 64278 us Read/Test 176636 us 
test Pattern 33333333 Write 64278 us Read/Test 176633 us 
test Pattern 0F0F0F0F Write 64278 us Read/Test 176634 us 
test Pattern 00FF00FF Write 64278 us Read/Test 176636 us 
test Pattern 0000FFFF Write 64279 us Read/Test 176634 us 
test Pattern AAAAAAAA Write 64279 us Read/Test 176636 us 
test Pattern CCCCCCCC Write 64278 us Read/Test 176636 us 
test Pattern F0F0F0F0 Write 64278 us Read/Test 176633 us 
test Pattern FF00FF00 Write 64278 us Read/Test 176634 us 
test Pattern FFFF0000 Write 64279 us Read/Test 176635 us 
test Pattern FFFFFFFF Write 64279 us Read/Test 176636 us 
test Pattern 00000000 Write 64278 us Read/Test 176638 us 
test RndSeed 2976674124 Write 119371 us Read/Test 278054 us 
test RndSeed 1438200953 Write 118847 us Read/Test 278058 us 
test RndSeed 3413783263 Write 118846 us Read/Test 278058 us 
test RndSeed 1900517911 Write 119376 us Read/Test 278061 us 
test RndSeed 1227909400 Write 119375 us Read/Test 278059 us 
test RndSeed 276562754 Write 118846 us Read/Test 278055 us 
test RndSeed 146878114 Write 118846 us Read/Test 278060 us 
test RndSeed 615545407 Write 118847 us Read/Test 278055 us 
test RndSeed 110497896 Write 119378 us Read/Test 278058 us 
test RndSeed 74539250 Write 119367 us Read/Test 278057 us 
test RndSeed 4197336575 Write 119374 us Read/Test 278058 us 
test RndSeed 2280382233 Write 118847 us Read/Test 278060 us 
test RndSeed 542894183 Write 118847 us Read/Test 278056 us 
test RndSeed 3978544245 Write 118846 us Read/Test 278056 us 
test RndSeed 2315909796 Write 118846 us Read/Test 278058 us 
test RndSeed 3736286001 Write 118847 us Read/Test 278056 us 
test RndSeed 2876690683 Write 119356 us Read/Test 278056 us 
test RndSeed 215559886 Write 119372 us Read/Test 278058 us 
test RndSeed 539179291 Write 119357 us Read/Test 278061 us 
test RndSeed 537678650 Write 118846 us Read/Test 278058 us 
test RndSeed 4001405270 Write 118847 us Read/Test 278060 us 
test RndSeed 2169216599 Write 119366 us Read/Test 278057 us 
test RndSeed 4036891097 Write 118846 us Read/Test 278055 us 
test RndSeed 1535452389 Write 119380 us Read/Test 278057 us 
test RndSeed 2959727213 Write 119375 us Read/Test 278057 us 
test RndSeed 4219363395 Write 118846 us Read/Test 278056 us 
test RndSeed 1036929753 Write 118846 us Read/Test 278060 us 
test RndSeed 2125248865 Write 119352 us Read/Test 278055 us 
test RndSeed 3177905864 Write 118846 us Read/Test 278058 us 
test RndSeed 2399307098 Write 118846 us Read/Test 278057 us 
test RndSeed 3847634607 Write 119358 us Read/Test 278057 us 
test RndSeed 27467969 Write 119369 us Read/Test 278057 us 
test RndSeed 520563506 Write 119372 us Read/Test 278059 us 
test RndSeed 381313790 Write 118846 us Read/Test 278060 us 
test RndSeed 4174769276 Write 118846 us Read/Test 278056 us 
test RndSeed 3932189449 Write 118846 us Read/Test 278058 us 
test RndSeed 4079717394 Write 118846 us Read/Test 278058 us 
test RndSeed 868357076 Write 118847 us Read/Test 278056 us 
test RndSeed 2474062993 Write 118847 us Read/Test 278057 us 
test RndSeed 1502682190 Write 118847 us Read/Test 278057 us 
test RndSeed 2471230478 Write 118846 us Read/Test 278054 us 
test RndSeed 85016565 Write 118846 us Read/Test 278059 us 
test RndSeed 1427530695 Write 118846 us Read/Test 278055 us 
test RndSeed 1100533073 Write 118846 us Read/Test 278059 us 
 test ran for 20.60 seconds
All memory tests passed :-)

defragster · Dec 25, 2023

mjs513 said:
@defragster - @Dogbone06

Created a version 1 of the Teensy_sdram sketch that cleans code up a little and added the test cases that are in the EVKB example.

Be interesting to see if it works I did check to see if it compiles without errors.

Merry Christmas

that works too! Added code was seen when doing posted sketch for prior post.
BTW @mjs513 - thanks for: By the Way.... Happy Anniversary!!!!

This lame (

) test looks at 4KB cool test above does 16 MB to match PSRAM.
> below DOUBLED and tested across all 32MB!


SDRAM Init Experiment
:-)

 SDRAM Memory 32 bit Write Start, Start Address 0x80000000, Data Length 4096 !
    SDRAM Memory 32 bit Write Time (uS) 62

 SDRAM Read 32 bit Data Start, Start Address 0x80000000, Data Length 4096 !
    SDRAM Memory 32 bit Read Time (uS) 171

 SDRAM 32 bit Data Write and Read Compare Start!
    SDRAM Memory 32 bit R/W Time (uS) 27
 SDRAM 32 bit Data Write and Read Compare Succeed!

 SDRAM Memory 16 bit Write Start, Start Address 0x80000000, Data Length 4096 !
    SDRAM Memory 16 bit Write Time (uS) 21
 SDRAM Read 16 bit Data Start, Start Address 0x80000000, Data Length 4096 !

 SDRAM Memory 16 bit Read Time (uS) 14
 SDRAM 16 bit Data Write and Read Compare Start!
     SDRAM Memory 16 bit Read/Write Time (uS) 28
 SDRAM 16 bit Data Write and Read Compare Succeed!

 SDRAM Memory 8 bit Write Start, Start Address 0x80000000, Data Length 4096 !
    SDRAM Memory 8 bit Write Time (uS) 28
 SDRAM Read 8 bit Data Start, Start Address 0x80000000, Data Length 4096 !
    SDRAM Memory 8 bit Read Time (uS) 14
 SDRAM 8 bit Data Write and Read Compare Start!

 SDRAM 8 bit Data Write and Read Compare Succeed!
    SDRAM Memory 8 bit Read/Write Time (uS) 31
 SDRAM Example End.

32MB TESTED and WORKING - in a hacky way needing many hours of work to be a REAL board:
NOTE: uploaded code noted in prior post tested to count FAILS and then enumerate any that fail when that happens
Also: fixed PATTERN write at 248 MB/sec and read/test at 90.5817 MB/SEC {need to add that CALC to the output}


SDRAM Init Experiment
:-)
Compile Time:: T:\T_Drive\tCode\RAM\teensyEVKB_xRAM_memtest\teensyEVKB_xRAM_memtest.ino Dec 25 2023 13:29:59
EXTMEM Memory Test, 32 Mbyte
EXTMEM Memory begin, 80000000
EXTMEM Memory end, 82000000
...
test Pattern 5A698421 Write 128759 us Read/Test 353272 us
test Pattern 55555555 Write 128658 us Read/Test 353267 us
test Pattern 33333333 Write 128658 us Read/Test 353267 us
test Pattern 0F0F0F0F Write 128658 us Read/Test 353271 us
test Pattern 00FF00FF Write 128657 us Read/Test 353268 us
test Pattern 0000FFFF Write 128657 us Read/Test 353278 us
test Pattern AAAAAAAA Write 128658 us Read/Test 353267 us
test Pattern CCCCCCCC Write 128657 us Read/Test 353270 us
test Pattern F0F0F0F0 Write 128658 us Read/Test 353271 us
test Pattern FF00FF00 Write 128658 us Read/Test 353271 us
test Pattern FFFF0000 Write 128657 us Read/Test 353265 us
test Pattern FFFFFFFF Write 128657 us Read/Test 353265 us
test Pattern 00000000 Write 128657 us Read/Test 353272 us
test RndSeed 2976674124 Write 237690 us Read/Test 556117 us
test RndSeed 1438200953 Write 238736 us Read/Test 556114 us
test RndSeed 3413783263 Write 237690 us Read/Test 556115 us
test RndSeed 1900517911 Write 237691 us Read/Test 556119 us
test RndSeed 1227909400 Write 238759 us Read/Test 556114 us
test RndSeed 276562754 Write 237689 us Read/Test 556114 us
test RndSeed 146878114 Write 237691 us Read/Test 556118 us
test RndSeed 615545407 Write 237690 us Read/Test 556115 us
test RndSeed 110497896 Write 237691 us Read/Test 556121 us
test RndSeed 74539250 Write 237690 us Read/Test 556115 us
test RndSeed 4197336575 Write 238770 us Read/Test 556115 us
test RndSeed 2280382233 Write 237690 us Read/Test 556114 us
test RndSeed 542894183 Write 237691 us Read/Test 556115 us
test RndSeed 3978544245 Write 237690 us Read/Test 556115 us
test RndSeed 2315909796 Write 237691 us Read/Test 556117 us
test RndSeed 3736286001 Write 237690 us Read/Test 556118 us
test RndSeed 2876690683 Write 238749 us Read/Test 556119 us
test RndSeed 215559886 Write 237691 us Read/Test 556116 us
test RndSeed 539179291 Write 237690 us Read/Test 556119 us
test RndSeed 537678650 Write 238746 us Read/Test 556115 us
test RndSeed 4001405270 Write 237691 us Read/Test 556114 us
test RndSeed 2169216599 Write 238751 us Read/Test 556113 us
test RndSeed 4036891097 Write 237691 us Read/Test 556115 us
test RndSeed 1535452389 Write 237691 us Read/Test 556118 us
test RndSeed 2959727213 Write 237690 us Read/Test 556119 us
test RndSeed 4219363395 Write 237690 us Read/Test 556116 us
test RndSeed 1036929753 Write 237690 us Read/Test 556116 us
test RndSeed 2125248865 Write 238748 us Read/Test 556112 us
test RndSeed 3177905864 Write 237691 us Read/Test 556116 us
test RndSeed 2399307098 Write 237691 us Read/Test 556115 us
test RndSeed 3847634607 Write 237690 us Read/Test 556115 us
test RndSeed 27467969 Write 237690 us Read/Test 556116 us
test RndSeed 520563506 Write 238733 us Read/Test 556120 us
test RndSeed 381313790 Write 238746 us Read/Test 556115 us
test RndSeed 4174769276 Write 237690 us Read/Test 556115 us
test RndSeed 3932189449 Write 237690 us Read/Test 556114 us
test RndSeed 4079717394 Write 237690 us Read/Test 556116 us
test RndSeed 868357076 Write 237691 us Read/Test 556115 us
test RndSeed 2474062993 Write 237690 us Read/Test 556116 us
test RndSeed 1502682190 Write 237690 us Read/Test 556120 us
test RndSeed 2471230478 Write 237690 us Read/Test 556118 us
test RndSeed 85016565 Write 237690 us Read/Test 556119 us
test RndSeed 1427530695 Write 237690 us Read/Test 556117 us
test RndSeed 1100533073 Write 237691 us Read/Test 556115 us
 test ran for 41.20 seconds
All memory tests passed :-)

mjs513 · Dec 25, 2023

@defragster - thanks for testing looking good. Will experiment more when I get the board.

defragster said:
many hours of work to be a REAL board:

Agree but at least we now know that SDRAM works with the current board. So will make it easier to debug whether its an issue with the added code to make it a board or not.

Think I am done for the night

EDIT: looks faster than on the EVKB

Call to arms | Teensy + SDRAM = true

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